[FFmpeg-devel] Discrepancy between comments for AVX512 flags

[FFmpeg-devel] Discrepancy between comments for AVX512 flags

[James Darnley]

While cherry-picking some stuff for avx512 I have noticed that ffmpeg 
has a discrepancy in the comments for the two avx512 flags.

Lets start with the public header
> libavutil/cpu.h
>   56│ #define AV_CPU_FLAG_AVX512     0x100000 ///< AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used
>   57│ #define AV_CPU_FLAG_AVX512ICL  0x200000 ///< F/CD/BW/DQ/VL/VNNI/IFMA/VBMI/VBMI2/VPOPCNTDQ/BITALG/GFNI/VAES/VPCLMULQDQ

This seem to imply the first only detects ZMM support and the second 
groups all instruction sets together.  This appears to be different to 
what we imply in internal code
> libavutil/x86/cpu.c
>  151│ #if HAVE_AVX512 /* F, CD, BW, DQ, VL */
> libavutil/x86/x86inc.asm
>  840│ %assign cpuflags_avx512    (1<<20)| cpuflags_avx2 ; F, CD, BW, DQ, VL     

The detection code itself has
> libavutil/x86/cpu.c
>  151│ #if HAVE_AVX512 /* F, CD, BW, DQ, VL */
>  152│         if ((xcr0_lo & 0xe0) == 0xe0) { /* OPMASK/ZMM state */
>  153│             if ((rval & AV_CPU_FLAG_AVX2) && (ebx & 0xd0030000) == 0xd0030000) {
>  154│                 rval |= AV_CPU_FLAG_AVX512;
>  155│ #if HAVE_AVX512ICL
>  156│                 if ((ebx & 0xd0200000) == 0xd0200000 && (ecx & 0x5f42) == 0x5f42)
>  157│                     rval |= AV_CPU_FLAG_AVX512ICL;

If you decode the bits being checked you'll see that the base avx512 
checks ebx for F DQ CD BW VL and avx512icl checks ebx for IFMA CD BW VL 
and ecx for VBMI VBMI2 GFNI VAES VPCLMULQDQ VNNI BITALG VPOPCNTDQ.  The 
first matches what the internal comments imply.

Part of the difference is my fault and dates from when the flag was 
first added.

Has there been a discussion about which features should go with which flag?
_______________________________________________
ffmpeg-devel mailing list
ffmpeg-devel@ffmpeg.org
https://ffmpeg.org/mailman/listinfo/ffmpeg-devel

To unsubscribe, visit link above, or email
ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe".

Re: [FFmpeg-devel] Discrepancy between comments for AVX512 flags

[Hendrik Leppkes]

On Sat, Aug 27, 2022 at 12:04 AM James Darnley <jdarnley@obe.tv> wrote:
>
> Has there been a discussion about which features should go with which flag?

I think the feature selection is fine as-is, if you want to clarify
the comments go ahead. AVX512 wouldn't be useful with a subset even
smaller then what the plain AVX512 is looking for (there is also no
CPUs with any smaller set, afaik), and most would even agree that the
ICL set is the minimum they would be developing for.

- Hendrik
_______________________________________________
ffmpeg-devel mailing list
ffmpeg-devel@ffmpeg.org
https://ffmpeg.org/mailman/listinfo/ffmpeg-devel

To unsubscribe, visit link above, or email
ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe".

Re: [FFmpeg-devel] Discrepancy between comments for AVX512 flags

[Henrik Gramner]

> On Sat, Aug 27, 2022 at 12:04 AM James Darnley <jdarnley@obe.tv> wrote:
> I think the feature selection is fine as-is, if you want to clarify
> the comments go ahead. AVX512 wouldn't be useful with a subset even
> smaller then what the plain AVX512 is looking for (there is also no
> CPUs with any smaller set, afaik), and most would even agree that the
> ICL set is the minimum they would be developing for.

To elaborate a bit further, the base AVX512 set is what Skylake
supports, and AVX51ICL is what Ice Lake supports. As far as I know,
Zen 4 will also support all the instructions Ice Lake supports, so
that should cover most systems.

We don't really care about Xeon Phi, so the Skylake subset is the de
facto minimum baseline.

This was done to get more manageable subsets that groups together
useful instructions in a way that maps reasonably well to real-world
hardware, in order to avoid having to deal with a dozen different
permutations.

There exists hardware which have instruction sets that fall outside
those two subsets, e.g. some Xeon Skylake-derivatives also has VNNI in
addition to the base Skylake subset and Tiger Lake has VP2INTERSECT,
but all things considered I consider the current design to be the best
compromise.

I'm sure Intel and AMD will add more instruction sets over time, so
we'll probably add new subsets in the future if/when there's a need
for it.

Henrik
_______________________________________________
ffmpeg-devel mailing list
ffmpeg-devel@ffmpeg.org
https://ffmpeg.org/mailman/listinfo/ffmpeg-devel

To unsubscribe, visit link above, or email
ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe".