From: Henrik Gramner <henrik@gramner.com>
To: FFmpeg development discussions and patches <ffmpeg-devel@ffmpeg.org>
Subject: Re: [FFmpeg-devel] Discrepancy between comments for AVX512 flags
Date: Sat, 27 Aug 2022 14:15:21 +0200
Message-ID: <CAFGUN0rCcELQniApPN0iD4wK7rQ_Bti6H0gxLT54xRMVq8QD7Q@mail.gmail.com> (raw)
In-Reply-To: <CA+anqdxicMfSRgDEkJbwH8JnX9j+R7r1F=QX+Gfs3Oh=FVp2kg@mail.gmail.com>
> On Sat, Aug 27, 2022 at 12:04 AM James Darnley <jdarnley@obe.tv> wrote:
> I think the feature selection is fine as-is, if you want to clarify
> the comments go ahead. AVX512 wouldn't be useful with a subset even
> smaller then what the plain AVX512 is looking for (there is also no
> CPUs with any smaller set, afaik), and most would even agree that the
> ICL set is the minimum they would be developing for.
To elaborate a bit further, the base AVX512 set is what Skylake
supports, and AVX51ICL is what Ice Lake supports. As far as I know,
Zen 4 will also support all the instructions Ice Lake supports, so
that should cover most systems.
We don't really care about Xeon Phi, so the Skylake subset is the de
facto minimum baseline.
This was done to get more manageable subsets that groups together
useful instructions in a way that maps reasonably well to real-world
hardware, in order to avoid having to deal with a dozen different
permutations.
There exists hardware which have instruction sets that fall outside
those two subsets, e.g. some Xeon Skylake-derivatives also has VNNI in
addition to the base Skylake subset and Tiger Lake has VP2INTERSECT,
but all things considered I consider the current design to be the best
compromise.
I'm sure Intel and AMD will add more instruction sets over time, so
we'll probably add new subsets in the future if/when there's a need
for it.
Henrik
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prev parent reply other threads:[~2022-08-27 12:15 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 22:01 James Darnley
2022-08-27 0:14 ` Hendrik Leppkes
2022-08-27 12:15 ` Henrik Gramner [this message]
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