From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org [79.124.17.100]) by master.gitmailbox.com (Postfix) with ESMTP id E1E244033B for ; Mon, 20 Dec 2021 14:21:40 +0000 (UTC) Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 6D9F368AE5D; Mon, 20 Dec 2021 16:21:38 +0200 (EET) Received: from mail-qt1-f180.google.com (mail-qt1-f180.google.com [209.85.160.180]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTPS id 5CCEF68A8EE for ; Mon, 20 Dec 2021 16:21:32 +0200 (EET) Received: by mail-qt1-f180.google.com with SMTP id m25so9791951qtq.13 for ; Mon, 20 Dec 2021 06:21:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=message-id:date:mime-version:user-agent:subject:content-language:to :references:from:in-reply-to:content-transfer-encoding; bh=hXRKX/XeSB198Rb55LgxHwL+yP3FVXeKc5u8TA6PWPU=; b=gTFKVXdYyiCUK8O9jp/ZNnaKYVk/YJO5Lo7ZdOEoCozn1w4lg8MTjNJVzbwnqBNRN/ aSljCpPrXRig/5Dxbdj5lxBKqzvjnbIZosmdNkU5EzHvrNryzieFj/XXUx8sLAXqDD4I 7M1rZmO2aV/JEpSSfZ29UoV04ctt8nfb9cr1BeunGzkeyQXbqgWNMimIW0YnO+m2U+2K RYxAoIZwxnlsNKdPlUtTKPN8FPnJnsojYqm+6H3wBqT9cAKm+yxd9rI3nWzm4Z2FkbZk Fh6gkRgBWeb77FLUMhDK/74S7gxMHVm6CVT7VJnit1YXvZWj/vH9Q3cBD8PdU/9pMFCy a0OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:references:from:in-reply-to :content-transfer-encoding; bh=hXRKX/XeSB198Rb55LgxHwL+yP3FVXeKc5u8TA6PWPU=; b=oURIeS/ZnSc6uUj3kYbYNGUZwt/qwTVFCantTsL4egJKCjOc283wYM1moxq7+eIF2f Wfgcikyp1rJ0tKCXU4tZrIxmbgpvgK+wlYihNgvmY7midjWX0uGvejbaQrUGcZ45rsbl H9GYh9Cp5I0RB2TrmWV+tWc4XJx32+FVP5Wi+JTjv64JPBg4ms8XYGukCRpFdO8fICmC G2oDH4ptLiPMAuY5dpgEw0G7AlwphB441CsqmNA9ZzIULZQJRKictLFhg1fd0Adt1Flo vITPprUXhc6Ges6Gpgp2rN+g68NBpq2mbD0BpWYoDIH5hGEocIGzxqhcVKBSrYOvWNlW 96TQ== X-Gm-Message-State: AOAM533jDy1VVCA2v1Z2jV2z0UrfsssnDsKZjs72z97Lgqw5H+j3knIP QsvOs00zW4kCOs1lvxtwMc7TI/HsQUdIxA== X-Google-Smtp-Source: ABdhPJyQZ4q0y0CqX/iqjy/mwkiQqzhfUVvlPrHtypLu6oXh+cEsaG632qAYSDPO0VtJbmmR0rkKhA== X-Received: by 2002:aed:30a3:: with SMTP id 32mr12475215qtf.660.1640010090591; Mon, 20 Dec 2021 06:21:30 -0800 (PST) Received: from [192.168.0.13] ([181.170.250.138]) by smtp.gmail.com with ESMTPSA id br43sm11668097qkb.57.2021.12.20.06.21.29 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Dec 2021 06:21:30 -0800 (PST) Message-ID: <8424d6a1-df63-954e-6823-740bf1fcb891@gmail.com> Date: Mon, 20 Dec 2021 11:21:28 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Content-Language: en-US To: ffmpeg-devel@ffmpeg.org References: <20211220135627.615097-1-alankelly@google.com> From: James Almer In-Reply-To: <20211220135627.615097-1-alankelly@google.com> Subject: Re: [FFmpeg-devel] [PATCH 1/2] libavutil/cpu: Add AV_CPU_FLAG_SLOW_GATHER. X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" Archived-At: List-Archive: List-Post: On 12/20/2021 10:56 AM, Alan Kelly wrote: > This flag is set on Haswell and earlier and all AMD cpus. > --- > As discussed on IRC last week. > libavutil/cpu.h | 57 +++++++++++++++++++++++---------------------- > libavutil/x86/cpu.c | 13 ++++++++++- > 2 files changed, 41 insertions(+), 29 deletions(-) > > diff --git a/libavutil/cpu.h b/libavutil/cpu.h > index ae443eccad..4272d11d73 100644 > --- a/libavutil/cpu.h > +++ b/libavutil/cpu.h > @@ -26,34 +26,35 @@ > #define AV_CPU_FLAG_FORCE 0x80000000 /* force usage of selected flags (OR) */ > > /* lower 16 bits - CPU features */ > -#define AV_CPU_FLAG_MMX 0x0001 ///< standard MMX > -#define AV_CPU_FLAG_MMXEXT 0x0002 ///< SSE integer functions or AMD MMX ext > -#define AV_CPU_FLAG_MMX2 0x0002 ///< SSE integer functions or AMD MMX ext > -#define AV_CPU_FLAG_3DNOW 0x0004 ///< AMD 3DNOW > -#define AV_CPU_FLAG_SSE 0x0008 ///< SSE functions > -#define AV_CPU_FLAG_SSE2 0x0010 ///< PIV SSE2 functions > -#define AV_CPU_FLAG_SSE2SLOW 0x40000000 ///< SSE2 supported, but usually not faster > - ///< than regular MMX/SSE (e.g. Core1) > -#define AV_CPU_FLAG_3DNOWEXT 0x0020 ///< AMD 3DNowExt > -#define AV_CPU_FLAG_SSE3 0x0040 ///< Prescott SSE3 functions > -#define AV_CPU_FLAG_SSE3SLOW 0x20000000 ///< SSE3 supported, but usually not faster > - ///< than regular MMX/SSE (e.g. Core1) > -#define AV_CPU_FLAG_SSSE3 0x0080 ///< Conroe SSSE3 functions > -#define AV_CPU_FLAG_SSSE3SLOW 0x4000000 ///< SSSE3 supported, but usually not faster > -#define AV_CPU_FLAG_ATOM 0x10000000 ///< Atom processor, some SSSE3 instructions are slower > -#define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions > -#define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions > -#define AV_CPU_FLAG_AESNI 0x80000 ///< Advanced Encryption Standard functions > -#define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used > -#define AV_CPU_FLAG_AVXSLOW 0x8000000 ///< AVX supported, but slow when using YMM registers (e.g. Bulldozer) > -#define AV_CPU_FLAG_XOP 0x0400 ///< Bulldozer XOP functions > -#define AV_CPU_FLAG_FMA4 0x0800 ///< Bulldozer FMA4 functions > -#define AV_CPU_FLAG_CMOV 0x1000 ///< supports cmov instruction > -#define AV_CPU_FLAG_AVX2 0x8000 ///< AVX2 functions: requires OS support even if YMM registers aren't used > -#define AV_CPU_FLAG_FMA3 0x10000 ///< Haswell FMA3 functions > -#define AV_CPU_FLAG_BMI1 0x20000 ///< Bit Manipulation Instruction Set 1 > -#define AV_CPU_FLAG_BMI2 0x40000 ///< Bit Manipulation Instruction Set 2 > -#define AV_CPU_FLAG_AVX512 0x100000 ///< AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used > +#define AV_CPU_FLAG_MMX 0x0001 ///< standard MMX > +#define AV_CPU_FLAG_MMXEXT 0x0002 ///< SSE integer functions or AMD MMX ext > +#define AV_CPU_FLAG_MMX2 0x0002 ///< SSE integer functions or AMD MMX ext > +#define AV_CPU_FLAG_3DNOW 0x0004 ///< AMD 3DNOW > +#define AV_CPU_FLAG_SSE 0x0008 ///< SSE functions > +#define AV_CPU_FLAG_SSE2 0x0010 ///< PIV SSE2 functions > +#define AV_CPU_FLAG_SSE2SLOW 0x40000000 ///< SSE2 supported, but usually not faster > + ///< than regular MMX/SSE (e.g. Core1) > +#define AV_CPU_FLAG_3DNOWEXT 0x0020 ///< AMD 3DNowExt > +#define AV_CPU_FLAG_SSE3 0x0040 ///< Prescott SSE3 functions > +#define AV_CPU_FLAG_SSE3SLOW 0x20000000 ///< SSE3 supported, but usually not faster > + ///< than regular MMX/SSE (e.g. Core1) > +#define AV_CPU_FLAG_SSSE3 0x0080 ///< Conroe SSSE3 functions > +#define AV_CPU_FLAG_SSSE3SLOW 0x4000000 ///< SSSE3 supported, but usually not faster > +#define AV_CPU_FLAG_ATOM 0x10000000 ///< Atom processor, some SSSE3 instructions are slower > +#define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions > +#define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions > +#define AV_CPU_FLAG_AESNI 0x80000 ///< Advanced Encryption Standard functions > +#define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used > +#define AV_CPU_FLAG_AVXSLOW 0x8000000 ///< AVX supported, but slow when using YMM registers (e.g. Bulldozer) > +#define AV_CPU_FLAG_XOP 0x0400 ///< Bulldozer XOP functions > +#define AV_CPU_FLAG_FMA4 0x0800 ///< Bulldozer FMA4 functions > +#define AV_CPU_FLAG_CMOV 0x1000 ///< supports cmov instruction > +#define AV_CPU_FLAG_AVX2 0x8000 ///< AVX2 functions: requires OS support even if YMM registers aren't used > +#define AV_CPU_FLAG_FMA3 0x10000 ///< Haswell FMA3 functions > +#define AV_CPU_FLAG_BMI1 0x20000 ///< Bit Manipulation Instruction Set 1 > +#define AV_CPU_FLAG_BMI2 0x40000 ///< Bit Manipulation Instruction Set 2 > +#define AV_CPU_FLAG_AVX512 0x100000 ///< AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used > +#define AV_CPU_FLAG_SLOW_GATHER 0x2000000 ///< CPU has slow gathers. Don't re-indent the other flags. It will affect git blame output. > > #define AV_CPU_FLAG_ALTIVEC 0x0001 ///< standard > #define AV_CPU_FLAG_VSX 0x0002 ///< ISA 2.06 > diff --git a/libavutil/x86/cpu.c b/libavutil/x86/cpu.c > index bcd41a50a2..5770ecec72 100644 > --- a/libavutil/x86/cpu.c > +++ b/libavutil/x86/cpu.c > @@ -146,8 +146,16 @@ int ff_get_cpu_flags_x86(void) > if (max_std_level >= 7) { > cpuid(7, eax, ebx, ecx, edx); > #if HAVE_AVX2 > - if ((rval & AV_CPU_FLAG_AVX) && (ebx & 0x00000020)) > + if ((rval & AV_CPU_FLAG_AVX) && (ebx & 0x00000020)) { > rval |= AV_CPU_FLAG_AVX2; > + cpuid(1, eax, ebx, ecx, std_caps); > + family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff); > + model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0); > + /* Haswell and earlier has slow gather */ Afaik Haswell is the first CPU with gathers, so this comment is odd. Is there another CPU this check below will trigger for? > + if(family == 6 && model < 70) > + rval |= AV_CPU_FLAG_SLOW_GATHER; > + } > + > #if HAVE_AVX512 /* F, CD, BW, DQ, VL */ > if ((xcr0_lo & 0xe0) == 0xe0) { /* OPMASK/ZMM state */ > if ((rval & AV_CPU_FLAG_AVX2) && (ebx & 0xd0030000) == 0xd0030000) > @@ -196,6 +204,9 @@ int ff_get_cpu_flags_x86(void) > used unless explicitly disabled by checking AV_CPU_FLAG_AVXSLOW. */ > if ((family == 0x15 || family == 0x16) && (rval & AV_CPU_FLAG_AVX)) > rval |= AV_CPU_FLAG_AVXSLOW; > + > + /* AMD cpus have slow gather */ > + rval |= AV_CPU_FLAG_SLOW_GATHER; Don't unconditionally enable this for every CPU. Do it only for those with AVX2. if (rval & AV_CPU_FLAG_AVX2) rval |= AV_CPU_FLAG_SLOW_GATHER; > } > > /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be _______________________________________________ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe".