From: "Rémi Denis-Courmont" <remi@remlab.net>
To: FFmpeg development discussions and patches <ffmpeg-devel@ffmpeg.org>
Subject: Re: [FFmpeg-devel] [PATCH] lavc/vc1dsp: R-V V inv_trans
Date: Tue, 05 Dec 2023 22:10:58 +0200
Message-ID: <3629844.N5QbZPjnrc@basile.remlab.net> (raw)
In-Reply-To: <CAEa-L+tfsDy=cP+2e_DMLyuHm4H74MNy72XxK+dFGVB9WpbfVA@mail.gmail.com>
Le tiistaina 5. joulukuuta 2023, 21.25.12 EET flow gg a écrit :
> > This block can be folded into the next. You don't need to check VLENB
>
> twice.
>
> Changed.
>
> > Instruction scheduling could be better, especially on in-order CPUs.
>
> I put the vload at the front, and then proceeded with the t2 operation, but
> I'm not sure...
>
> > You don't need to reset the AVL here, just pass zero.
>
> Changed.
>
> > vsetivli
>
> Changed.
You changed more than I asked for. The immediate AVL is a 5-bit unsigned
integer, so it should not be possible to assemble 32 or 64, unless you have a
preprocessor that silently rewrites `vsetivli` into `vsetvli` (If so, that
sounds very iffy because `vsetivli zero` has no scratch X register to work
with).
FWIW CanMV-K230 boards are on sale for under 500 RMB.
--
レミ・デニ-クールモン
http://www.remlab.net/
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next prev parent reply other threads:[~2023-12-05 20:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-03 14:40 flow gg
2023-12-03 17:17 ` Rémi Denis-Courmont
2023-12-04 8:48 ` flow gg
2023-12-04 15:15 ` Rémi Denis-Courmont
2023-12-04 21:14 ` flow gg
2023-12-05 5:25 ` flow gg
2023-12-05 16:41 ` Rémi Denis-Courmont
2023-12-05 19:25 ` flow gg
2023-12-05 20:10 ` Rémi Denis-Courmont [this message]
2023-12-05 23:50 ` flow gg
2023-12-06 2:23 ` flow gg
2023-12-08 7:31 ` flow gg
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