Re: [FFmpeg-devel] RISC-V vector DSP functions: Motivation for commit 446b009

["Rémi Denis-Courmont" <remi@remlab.net>]

(Updating an old thread)

Le perjantaina 19. tammikuuta 2024, 19.14.02 EEST Rémi Denis-Courmont a écrit 
:
> Hi,
> 
> Le perjantaina 19. tammikuuta 2024, 17.30.00 EET Michael Platzer via ffmpeg-
> devel a écrit :
> > Commit 446b0090cbb66ee614dcf6ca79c78dc8eb7f0e37 by Remi Denis-Courmont has
> > replaced RISC-V vector loads and stores with negative stride with vrgather
> > (generalized permutation within vector registers) instructions in order to
> > reverse the elements in a vector register. The commit message explains
> > that
> > this change was done, but it does not explain why.
> 
> It was faster on what the best approximation of real hardware available at
> the time, i.e. a Sipeed Lichee Pi4A board. There are no benchmarks in the
> commit because I don't like to publish benchmarks collected from
> prototypes.

FWIW, it still seems true on SpacemiT X60 (BananaPi-F3).

On that hardware, strided load/stores scale linear to the number of elements, 
as you'd expect, with no optimisations for minus one stride (or more 
accurately, minus element byte site). Vector gathers scale quadratic.

So for sufficiently large vectors, strided load/stores would presumably be 
faster. But on real hardware with relatively small vector sizes, highest 
bandwidth is achieved by unit-strided load/stores and vector gather with 
LMUL=1.

-- 
雷米‧德尼-库尔蒙
http://www.remlab.net/



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