[FFmpeg-devel] [PATCHv2 1/4] lavc/vc1dsp: R-V V vc1_inv_trans_8x8

[FFmpeg-devel] [PATCHv2 1/4] lavc/vc1dsp: R-V V vc1_inv_trans_8x8

[Rémi Denis-Courmont]

T-Head C908 (cycles):
vc1dsp.vc1_inv_trans_8x8_c:       871.7
vc1dsp.vc1_inv_trans_8x8_rvv_i32: 286.7

---
Changes since version 1:
- Use fixed-point rounding instead of adding 4 or 64 explicitly.

---
 libavcodec/riscv/vc1dsp_init.c |   2 +
 libavcodec/riscv/vc1dsp_rvv.S  | 110 +++++++++++++++++++++++++++++++++
 2 files changed, 112 insertions(+)

diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c
index e4838fb347..b8a1015ce5 100644
--- a/libavcodec/riscv/vc1dsp_init.c
+++ b/libavcodec/riscv/vc1dsp_init.c
@@ -26,6 +26,7 @@
 #include "libavcodec/vc1.h"
 
 void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
+void ff_vc1_inv_trans_8x8_rvv(int16_t block[64]);
 void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
@@ -53,6 +54,7 @@ av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
 # if HAVE_RVV
     if (flags & AV_CPU_FLAG_RVV_I32) {
         if (ff_rv_vlen_least(128)) {
+            dsp->vc1_inv_trans_8x8 = ff_vc1_inv_trans_8x8_rvv;
             dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
             dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
             dsp->avg_vc1_mspel_pixels_tab[0][0] = ff_avg_pixels16x16_rvv;
diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S
index 8b3a830a4a..e15783d113 100644
--- a/libavcodec/riscv/vc1dsp_rvv.S
+++ b/libavcodec/riscv/vc1dsp_rvv.S
@@ -113,6 +113,116 @@ func ff_vc1_inv_trans_4x4_dc_rvv, zve32x
         ret
 endfunc
 
+        .variant_cc ff_vc1_inv_trans_8_rvv
+func ff_vc1_inv_trans_8_rvv, zve32x
+        li      t4, 12
+        vsll.vi v18, v6, 4
+        li      t2, 6
+        vmul.vx v8, v0, t4
+        li      t5, 15
+        vmul.vx v10, v4, t4
+        li      t3, 9
+        # t[2..5] = [6 9 12 15]
+        vsll.vi v12, v2, 4
+        vmul.vx v14, v6, t2
+        vmul.vx v16, v2, t2
+        vadd.vv v26, v12, v14 # t3
+        vadd.vv v24, v8, v10  # t1
+        vsub.vv v25, v8, v10  # t2
+        vsub.vv v27, v16, v18 # t4
+        vadd.vv v28, v24, v26 # t5
+        vsub.vv v31, v24, v26 # t8
+        vadd.vv v29, v25, v27 # t6
+        vsub.vv v30, v25, v27 # t7
+        vsll.vi v20, v1, 4
+        vmul.vx v21, v3, t5
+        vmul.vx v22, v5, t3
+        vsll.vi v23, v7, 2
+        vadd.vv v20, v20, v21
+        vadd.vv v22, v22, v23
+        vsll.vi v21, v3, 2
+        vadd.vv v16, v20, v22 # t1
+        vmul.vx v20, v1, t5
+        vsll.vi v22, v5, 4
+        vmul.vx v23, v7, t3
+        vsub.vv v20, v20, v21
+        vadd.vv v22, v22, v23
+        vsll.vi v21, v3, 4
+        vsub.vv v17, v20, v22 # t2
+        vmul.vx v20, v1, t3
+        vsll.vi v22, v5, 2
+        vmul.vx v23, v7, t5
+        vsub.vv v20, v20, v21
+        vadd.vv v22, v22, v23
+        vmul.vx v21, v3, t3
+        vadd.vv v18, v20, v22 # t3
+        vsll.vi v20, v1, 2
+        vmul.vx v22, v5, t5
+        vsll.vi v23, v7, 4
+        vsub.vv v20, v20, v21
+        vsub.vv v22, v22, v23
+        vadd.vv v0, v28, v16
+        vadd.vv v19, v20, v22 # t4
+        vadd.vv v1, v29, v17
+        vadd.vv v2, v30, v18
+        vadd.vv v3, v31, v19
+        vsub.vv v4, v31, v19
+        vsub.vv v5, v30, v18
+        vsub.vv v6, v29, v17
+        vsub.vv v7, v28, v16
+        jr      t0
+endfunc
+
+func ff_vc1_inv_trans_8x8_rvv, zve32x
+        csrwi    vxrm, 0
+        vsetivli zero, 8, e16, m1, ta, ma
+        addi     a1, a0, 1 * 8 * 2
+        vle16.v  v0, (a0)
+        addi     a2, a0, 2 * 8 * 2
+        vle16.v  v1, (a1)
+        addi     a3, a0, 3 * 8 * 2
+        vle16.v  v2, (a2)
+        addi     a4, a0, 4 * 8 * 2
+        vle16.v  v3, (a3)
+        addi     a5, a0, 5 * 8 * 2
+        vle16.v  v4, (a4)
+        addi     a6, a0, 6 * 8 * 2
+        vle16.v  v5, (a5)
+        addi     a7, a0, 7 * 8 * 2
+        vle16.v  v6, (a6)
+        vle16.v  v7, (a7)
+        jal      t0, ff_vc1_inv_trans_8_rvv
+        .irp n,0,1,2,3,4,5,6,7
+        vssra.vi v\n, v\n, 3
+        .endr
+        vsseg8e16.v v0, (a0)
+        .irp n,0,1,2,3,4,5,6,7
+        vle16.v  v\n, (a\n)
+        .endr
+        jal      t0, ff_vc1_inv_trans_8_rvv
+        vadd.vi  v4, v4, 1
+        vadd.vi  v5, v5, 1
+        vssra.vi v4, v4, 7
+        vssra.vi v5, v5, 7
+        vse16.v  v4, (a4)
+        vadd.vi  v6, v6, 1
+        vse16.v  v5, (a5)
+        vadd.vi  v7, v7, 1
+        vssra.vi v6, v6, 7
+        vssra.vi v7, v7, 7
+        vse16.v  v6, (a6)
+        vssra.vi v0, v0, 7
+        vse16.v  v7, (a7)
+        vssra.vi v1, v1, 7
+        vse16.v  v0, (a0)
+        vssra.vi v2, v2, 7
+        vse16.v  v1, (a1)
+        vssra.vi v3, v3, 7
+        vse16.v  v2, (a2)
+        vse16.v  v3, (a3)
+        ret
+endfunc
+
 .macro mspel_op op pos n1 n2
         add           t1, \pos, a2
         v\op\()e8.v   v\n1, (\pos)
-- 
2.45.1

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[FFmpeg-devel] [PATCHv2 2/4] lavc/vc1dsp: R-V V vc1_inv_trans_8x4

[Rémi Denis-Courmont]

T-Head C908 (cycles):
vc1dsp.vc1_inv_trans_8x4_c:       626.2
vc1dsp.vc1_inv_trans_8x4_rvv_i32: 215.2

---
Changes since version 1:
- Properly set VXRM (callee-clobbered).

---
 libavcodec/riscv/vc1dsp_init.c |  2 +
 libavcodec/riscv/vc1dsp_rvv.S  | 73 ++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)

diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c
index b8a1015ce5..e63870ad44 100644
--- a/libavcodec/riscv/vc1dsp_init.c
+++ b/libavcodec/riscv/vc1dsp_init.c
@@ -29,6 +29,7 @@ void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block
 void ff_vc1_inv_trans_8x8_rvv(int16_t block[64]);
 void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
+void ff_vc1_inv_trans_8x4_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_put_pixels16x16_rvi(uint8_t *dst, const uint8_t *src, ptrdiff_t line_size, int rnd);
 void ff_put_pixels8x8_rvi(uint8_t *dst, const uint8_t *src, ptrdiff_t line_size, int rnd);
@@ -55,6 +56,7 @@ av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
     if (flags & AV_CPU_FLAG_RVV_I32) {
         if (ff_rv_vlen_least(128)) {
             dsp->vc1_inv_trans_8x8 = ff_vc1_inv_trans_8x8_rvv;
+            dsp->vc1_inv_trans_8x4 = ff_vc1_inv_trans_8x4_rvv;
             dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
             dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
             dsp->avg_vc1_mspel_pixels_tab[0][0] = ff_avg_pixels16x16_rvv;
diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S
index e15783d113..d003185ade 100644
--- a/libavcodec/riscv/vc1dsp_rvv.S
+++ b/libavcodec/riscv/vc1dsp_rvv.S
@@ -173,6 +173,31 @@ func ff_vc1_inv_trans_8_rvv, zve32x
         jr      t0
 endfunc
 
+        .variant_cc ff_vc1_inv_trans_4_rvv
+func ff_vc1_inv_trans_4_rvv, zve32x
+        li      t3, 17
+        vmul.vx v8, v0, t3
+        li      t4, 22
+        vmul.vx v10, v2, t3
+        li      t2, 10
+        vmul.vx v14, v1, t4
+        vadd.vv v24, v8, v10  # t1
+        vsub.vv v25, v8, v10  # t2
+        vmul.vx v16, v3, t2
+        vmul.vx v18, v3, t4
+        vmul.vx v20, v1, t2
+        vadd.vv v26, v14, v16 # t3
+        vsub.vv v27, v18, v20 # t4
+        vadd.vv v0, v24, v26
+        vsub.vv v1, v25, v27
+        vadd.vv v2, v25, v27
+        vsub.vv v3, v24, v26
+        .irp    n,0,1,2,3
+        vssra.vx v\n, v\n, t1 # + 4 >> 3 or + 64 >> 7
+        .endr
+        jr      t0
+endfunc
+
 func ff_vc1_inv_trans_8x8_rvv, zve32x
         csrwi    vxrm, 0
         vsetivli zero, 8, e16, m1, ta, ma
@@ -223,6 +248,54 @@ func ff_vc1_inv_trans_8x8_rvv, zve32x
         ret
 endfunc
 
+func ff_vc1_inv_trans_8x4_rvv, zve32x
+        csrwi       vxrm, 0
+        vsetivli    zero, 4, e16, mf2, ta, ma
+        vlseg8e16.v v0, (a2)
+        jal         t0, ff_vc1_inv_trans_8_rvv
+        vsseg8e16.v v0, (a2)
+        addi        a3, a2, 1 * 8 * 2
+        vsetivli    zero, 8, e16, m1, ta, ma
+        vle16.v     v0, (a2)
+        addi        a4, a2, 2 * 8 * 2
+        vle16.v     v1, (a3)
+        addi        a5, a2, 3 * 8 * 2
+        vle16.v     v2, (a4)
+        vle16.v     v3, (a5)
+        .irp    n,0,1,2,3
+        # shift 4 vectors of 8 elems after transpose instead of 8 of 4
+        vssra.vi    v\n, v\n, 3
+        .endr
+        li          t1, 7
+        jal         t0, ff_vc1_inv_trans_4_rvv
+        add         a3, a1, a0
+        vle8.v      v8, (a0)
+        add         a4, a1, a3
+        vle8.v      v9, (a3)
+        add         a5, a1, a4
+        vle8.v      v10, (a4)
+        vle8.v      v11, (a5)
+        vsetvli     zero, zero, e8, mf2, ta, ma
+        vwaddu.wv   v0, v0, v8
+        vwaddu.wv   v1, v1, v9
+        vwaddu.wv   v2, v2, v10
+        vwaddu.wv   v3, v3, v11
+        vsetvli     zero, zero, e16, m1, ta, ma
+        .irp    n,0,1,2,3
+        vmax.vx     v\n, v\n, zero
+        .endr
+        vsetvli     zero, zero, e8, mf2, ta, ma
+        vnclipu.wi  v8, v0, 0
+        vnclipu.wi  v9, v1, 0
+        vse8.v      v8, (a0)
+        vnclipu.wi  v10, v2, 0
+        vse8.v      v9, (a3)
+        vnclipu.wi  v11, v3, 0
+        vse8.v      v10, (a4)
+        vse8.v      v11, (a5)
+        ret
+endfunc
+
 .macro mspel_op op pos n1 n2
         add           t1, \pos, a2
         v\op\()e8.v   v\n1, (\pos)
-- 
2.45.1

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[FFmpeg-devel] [PATCHv2 3/4] lavc/vc1dsp: R-V V vc1_inv_trans_4x8

[Rémi Denis-Courmont]

T-Head C908 (cycles):
vc1dsp.vc1_inv_trans_4x8_c: 653.2
vc1dsp.vc1_inv_trans_4x8_rvv_i32: 234.0
---
 libavcodec/riscv/vc1dsp_init.c |  2 +
 libavcodec/riscv/vc1dsp_rvv.S  | 77 ++++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c
index e63870ad44..cf9d42f377 100644
--- a/libavcodec/riscv/vc1dsp_init.c
+++ b/libavcodec/riscv/vc1dsp_init.c
@@ -28,6 +28,7 @@
 void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_8x8_rvv(int16_t block[64]);
 void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
+void ff_vc1_inv_trans_4x8_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_8x4_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
@@ -57,6 +58,7 @@ av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
         if (ff_rv_vlen_least(128)) {
             dsp->vc1_inv_trans_8x8 = ff_vc1_inv_trans_8x8_rvv;
             dsp->vc1_inv_trans_8x4 = ff_vc1_inv_trans_8x4_rvv;
+            dsp->vc1_inv_trans_4x8 = ff_vc1_inv_trans_4x8_rvv;
             dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
             dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
             dsp->avg_vc1_mspel_pixels_tab[0][0] = ff_avg_pixels16x16_rvv;
diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S
index d003185ade..e22950d25d 100644
--- a/libavcodec/riscv/vc1dsp_rvv.S
+++ b/libavcodec/riscv/vc1dsp_rvv.S
@@ -296,6 +296,83 @@ func ff_vc1_inv_trans_8x4_rvv, zve32x
         ret
 endfunc
 
+func ff_vc1_inv_trans_4x8_rvv, zve32x
+        li           a3, 8 * 2
+        csrwi        vxrm, 0
+        vsetivli     zero, 8, e16, m1, ta, ma
+        vlsseg4e16.v v0, (a2), a3
+        li           t1, 3
+        jal          t0, ff_vc1_inv_trans_4_rvv
+        addi         t1, a2, 1 * 8 * 2
+        vse16.v      v0, (a2)
+        addi         t2, a2, 2 * 8 * 2
+        vse16.v      v1, (t1)
+        addi         t3, a2, 3 * 8 * 2
+        vse16.v      v2, (t2)
+        vse16.v      v3, (t3)
+        vsetivli     zero, 4, e16, mf2, ta, ma
+        vlseg8e16.v  v0, (a2)
+        jal          t0, ff_vc1_inv_trans_8_rvv
+        vadd.vi      v4, v4, 1
+        add          t0, a1, a0
+        vadd.vi      v5, v5, 1
+        vadd.vi      v6, v6, 1
+        add          t1, a1, t0
+        vadd.vi      v7, v7, 1
+        vssra.vi     v0, v0, 7
+        add          t2, a1, t1
+        vssra.vi     v1, v1, 7
+        vssra.vi     v2, v2, 7
+        add          t3, a1, t2
+        vssra.vi     v3, v3, 7
+        vssra.vi     v4, v4, 7
+        add          t4, a1, t3
+        vssra.vi     v5, v5, 7
+        vssra.vi     v6, v6, 7
+        add          t5, a1, t4
+        vssra.vi     v7, v7, 7
+        vle8.v       v8, (a0)
+        add          t6, a1, t5
+        vle8.v       v9, (t0)
+        vle8.v       v10, (t1)
+        vle8.v       v11, (t2)
+        vle8.v       v12, (t3)
+        vle8.v       v13, (t4)
+        vle8.v       v14, (t5)
+        vle8.v       v15, (t6)
+        vsetvli      zero, zero, e8, mf4, ta, ma
+        vwaddu.wv    v0, v0, v8
+        vwaddu.wv    v1, v1, v9
+        vwaddu.wv    v2, v2, v10
+        vwaddu.wv    v3, v3, v11
+        vwaddu.wv    v4, v4, v12
+        vwaddu.wv    v5, v5, v13
+        vwaddu.wv    v6, v6, v14
+        vwaddu.wv    v7, v7, v15
+        vsetvli      zero, zero, e16, mf2, ta, ma
+        .irp    n,0,1,2,3,4,5,6,7
+        vmax.vx      v\n, v\n, zero
+        .endr
+        vsetvli      zero, zero, e8, mf4, ta, ma
+        vnclipu.wi   v8, v0, 0
+        vnclipu.wi   v9, v1, 0
+        vse8.v       v8, (a0)
+        vnclipu.wi   v10, v2, 0
+        vse8.v       v9, (t0)
+        vnclipu.wi   v11, v3, 0
+        vse8.v       v10, (t1)
+        vnclipu.wi   v12, v4, 0
+        vse8.v       v11, (t2)
+        vnclipu.wi   v13, v5, 0
+        vse8.v       v12, (t3)
+        vnclipu.wi   v14, v6, 0
+        vse8.v       v13, (t4)
+        vnclipu.wi   v15, v7, 0
+        vse8.v       v14, (t5)
+        vse8.v       v15, (t6)
+        ret
+endfunc
+
 .macro mspel_op op pos n1 n2
         add           t1, \pos, a2
         v\op\()e8.v   v\n1, (\pos)
-- 
2.45.1

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[FFmpeg-devel] [PATCHv2 4/4] lavc/vc1dsp: R-V V vc1_inv_trans_4x4

[Rémi Denis-Courmont]

T-Head C908 (cycles):
vc1dsp.vc1_inv_trans_4x4_c: 310.7
vc1dsp.vc1_inv_trans_4x4_rvv_i32: 120.0

We could use 1 `vlseg4e64.v` instead of 4 `vle16.v`, but that seems to
be about 7% slower.
---
 libavcodec/riscv/vc1dsp_init.c |  2 ++
 libavcodec/riscv/vc1dsp_rvv.S  | 47 ++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c
index cf9d42f377..de9002f395 100644
--- a/libavcodec/riscv/vc1dsp_init.c
+++ b/libavcodec/riscv/vc1dsp_init.c
@@ -32,6 +32,7 @@ void ff_vc1_inv_trans_4x8_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_8x4_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
+void ff_vc1_inv_trans_4x4_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
 void ff_put_pixels16x16_rvi(uint8_t *dst, const uint8_t *src, ptrdiff_t line_size, int rnd);
 void ff_put_pixels8x8_rvi(uint8_t *dst, const uint8_t *src, ptrdiff_t line_size, int rnd);
 void ff_avg_pixels16x16_rvv(uint8_t *dst, const uint8_t *src, ptrdiff_t line_size, int rnd);
@@ -59,6 +60,7 @@ av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
             dsp->vc1_inv_trans_8x8 = ff_vc1_inv_trans_8x8_rvv;
             dsp->vc1_inv_trans_8x4 = ff_vc1_inv_trans_8x4_rvv;
             dsp->vc1_inv_trans_4x8 = ff_vc1_inv_trans_4x8_rvv;
+            dsp->vc1_inv_trans_4x4 = ff_vc1_inv_trans_4x4_rvv;
             dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
             dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
             dsp->avg_vc1_mspel_pixels_tab[0][0] = ff_avg_pixels16x16_rvv;
diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S
index e22950d25d..03c942cba2 100644
--- a/libavcodec/riscv/vc1dsp_rvv.S
+++ b/libavcodec/riscv/vc1dsp_rvv.S
@@ -113,6 +113,8 @@ func ff_vc1_inv_trans_4x4_dc_rvv, zve32x
         ret
 endfunc
 
+#include "../../riscv-tests/debug.S"
+
         .variant_cc ff_vc1_inv_trans_8_rvv
 func ff_vc1_inv_trans_8_rvv, zve32x
         li      t4, 12
@@ -373,6 +375,51 @@ func ff_vc1_inv_trans_4x8_rvv, zve32x
         ret
 endfunc
 
+func ff_vc1_inv_trans_4x4_rvv, zve32x
+        li           a3, 8 * 2
+        csrwi        vxrm, 0
+        vsetivli     zero, 4, e16, mf2, ta, ma
+        vlsseg4e16.v v0, (a2), a3
+        li           t1, 3
+        jal          t0, ff_vc1_inv_trans_4_rvv
+        vsseg4e16.v  v0, (a2)
+        addi         t1, a2, 1 * 4 * 2
+        vle16.v      v0, (a2)
+        addi         t2, a2, 2 * 4 * 2
+        vle16.v      v1, (t1)
+        addi         t3, a2, 3 * 4 * 2
+        vle16.v      v2, (t2)
+        vle16.v      v3, (t3)
+        li           t1, 7
+        jal          t0, ff_vc1_inv_trans_4_rvv
+        add          t1, a1, a0
+        vle8.v       v8, (a0)
+        add          t2, a1, t1
+        vle8.v       v9, (t1)
+        add          t3, a1, t2
+        vle8.v       v10, (t2)
+        vle8.v       v11, (t3)
+        vsetvli      zero, zero, e8, mf4, ta, ma
+        vwaddu.wv    v0, v0, v8
+        vwaddu.wv    v1, v1, v9
+        vwaddu.wv    v2, v2, v10
+        vwaddu.wv    v3, v3, v11
+        vsetvli      zero, zero, e16, mf2, ta, ma
+        .irp    n,0,1,2,3
+        vmax.vx      v\n, v\n, zero
+        .endr
+        vsetvli      zero, zero, e8, mf4, ta, ma
+        vnclipu.wi   v8, v0, 0
+        vnclipu.wi   v9, v1, 0
+        vse8.v       v8, (a0)
+        vnclipu.wi   v10, v2, 0
+        vse8.v       v9, (t1)
+        vnclipu.wi   v11, v3, 0
+        vse8.v       v10, (t2)
+        vse8.v       v11, (t3)
+        ret
+endfunc
+
 .macro mspel_op op pos n1 n2
         add           t1, \pos, a2
         v\op\()e8.v   v\n1, (\pos)
-- 
2.45.1

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