From: "Rémi Denis-Courmont" <remi@remlab.net>
To: ffmpeg-devel@ffmpeg.org
Subject: [FFmpeg-devel] [PATCH 2/2] lavc/vp8dsp: restrict RVI optimisations
Date: Sat, 11 May 2024 18:51:42 +0300
Message-ID: <20240511155142.59542-2-remi@remlab.net> (raw)
In-Reply-To: <20240511155142.59542-1-remi@remlab.net>
They are actually awfully slow if the CPU does not support misaligned
accesses natively, so only use them if misaligned accesses are fast.
---
libavcodec/riscv/vp8dsp_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libavcodec/riscv/vp8dsp_init.c b/libavcodec/riscv/vp8dsp_init.c
index dc3e087f01..fe4fa5b867 100644
--- a/libavcodec/riscv/vp8dsp_init.c
+++ b/libavcodec/riscv/vp8dsp_init.c
@@ -45,7 +45,7 @@ av_cold void ff_vp78dsp_init_riscv(VP8DSPContext *c)
{
#if HAVE_RV
int flags = av_get_cpu_flags();
- if (flags & AV_CPU_FLAG_RVI) {
+ if (flags & AV_CPU_FLAG_RV_MISALIGNED) {
#if __riscv_xlen >= 64
c->put_vp8_epel_pixels_tab[0][0][0] = ff_put_vp8_pixels16_rvi;
c->put_vp8_epel_pixels_tab[1][0][0] = ff_put_vp8_pixels8_rvi;
--
2.43.0
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prev parent reply other threads:[~2024-05-11 15:52 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-11 15:51 [FFmpeg-devel] [PATCH 1/2] lavu/riscv: CPU flag for fast misaligned accesses Rémi Denis-Courmont
2024-05-11 15:51 ` Rémi Denis-Courmont [this message]
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