From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org [79.124.17.100]) by master.gitmailbox.com (Postfix) with ESMTP id 5745249E17 for ; Sat, 11 May 2024 15:51:52 +0000 (UTC) Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id D2BB168D4E5; Sat, 11 May 2024 18:51:49 +0300 (EEST) Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 1618068CDAC for ; Sat, 11 May 2024 18:51:43 +0300 (EEST) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id 7C0A2C006B for ; Sat, 11 May 2024 18:51:42 +0300 (EEST) From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= To: ffmpeg-devel@ffmpeg.org Date: Sat, 11 May 2024 18:51:41 +0300 Message-ID: <20240511155142.59542-1-remi@remlab.net> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 1/2] lavu/riscv: CPU flag for fast misaligned accesses X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" Archived-At: List-Archive: List-Post: --- libavutil/cpu.c | 1 + libavutil/cpu.h | 1 + libavutil/riscv/cpu.c | 3 +++ libavutil/tests/cpu.c | 3 ++- tests/checkasm/checkasm.c | 1 + 5 files changed, 8 insertions(+), 1 deletion(-) diff --git a/libavutil/cpu.c b/libavutil/cpu.c index 396eeb38d6..9ac2f01c20 100644 --- a/libavutil/cpu.c +++ b/libavutil/cpu.c @@ -193,6 +193,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s) { "zba", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_ADDR }, .unit = "flags" }, { "zbb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC }, .unit = "flags" }, { "zvbb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVBB }, .unit = "flags" }, + { "misaligned", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_MISALIGNED }, .unit = "flags" }, #endif { NULL }, }; diff --git a/libavutil/cpu.h b/libavutil/cpu.h index cc19828d4b..a25901433e 100644 --- a/libavutil/cpu.h +++ b/libavutil/cpu.h @@ -91,6 +91,7 @@ #define AV_CPU_FLAG_RVB_BASIC (1 << 7) ///< Basic bit-manipulations #define AV_CPU_FLAG_RVB_ADDR (1 << 8) ///< Address bit-manipulations #define AV_CPU_FLAG_RV_ZVBB (1 << 9) ///< Vector basic bit-manipulations +#define AV_CPU_FLAG_RV_MISALIGNED (1 <<10) ///< Fast misaligned accesses /** * Return the flags which specify extensions supported by the CPU. diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c index 6755f0df69..1fe1a397c4 100644 --- a/libavutil/riscv/cpu.c +++ b/libavutil/riscv/cpu.c @@ -52,6 +52,7 @@ int ff_get_cpu_flags_riscv(void) struct riscv_hwprobe pairs[] = { { RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0 }, { RISCV_HWPROBE_KEY_IMA_EXT_0, 0 }, + { RISCV_HWPROBE_KEY_CPUPERF_0, 0 }, }; if (__riscv_hwprobe(pairs, FF_ARRAY_ELEMS(pairs), 0, NULL, 0) == 0) { @@ -76,6 +77,8 @@ int ff_get_cpu_flags_riscv(void) if (pairs[1].value & RISCV_HWPROBE_EXT_ZVBB) ret |= AV_CPU_FLAG_RV_ZVBB; #endif + if (pairs[2].value & RISCV_HWPROBE_MISALIGNED_FAST) + ret |= AV_CPU_FLAG_RV_MISALIGNED; } else #endif #if HAVE_GETAUXVAL diff --git a/libavutil/tests/cpu.c b/libavutil/tests/cpu.c index 10e620963b..02b98682e3 100644 --- a/libavutil/tests/cpu.c +++ b/libavutil/tests/cpu.c @@ -94,7 +94,8 @@ static const struct { { AV_CPU_FLAG_RVV_F32, "zve32f" }, { AV_CPU_FLAG_RVV_I64, "zve64x" }, { AV_CPU_FLAG_RVV_F64, "zve64d" }, - { AV_CPU_FLAG_RV_ZVBB, "zvbb" }, + { AV_CPU_FLAG_RV_ZVBB, "zvbb" }, + { AV_CPU_FLAG_RV_MISALIGNED, "misaligned" }, #endif { 0 } }; diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c index 04f94f9d09..c6dc0cfa77 100644 --- a/tests/checkasm/checkasm.c +++ b/tests/checkasm/checkasm.c @@ -286,6 +286,7 @@ static const struct { { "RVVi64", "rvv_i64", AV_CPU_FLAG_RVV_I64 }, { "RVVf64", "rvv_f64", AV_CPU_FLAG_RVV_F64 }, { "RV_Zvbb", "rv_zvbb", AV_CPU_FLAG_RV_ZVBB }, + { "misaligned", "misaligned", AV_CPU_FLAG_RV_MISALIGNED }, #elif ARCH_MIPS { "MMI", "mmi", AV_CPU_FLAG_MMI }, { "MSA", "msa", AV_CPU_FLAG_MSA }, -- 2.43.0 _______________________________________________ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe".