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From: Peiting Shen <shenpeiting@eswincomputing.com>
To: ffmpeg-devel@ffmpeg.org
Cc: Shen Peiting <shenpeiting@eswincomputing.com>
Subject: [FFmpeg-devel] [PATCH 4/6] lavc/ac3dsp: RISC-V V ac3_sum_square_butterfly_float
Date: Thu, 15 Jun 2023 10:36:43 +0000
Message-ID: <20230615103645.25778-5-shenpeiting@eswincomputing.com> (raw)
In-Reply-To: <20230615103645.25778-1-shenpeiting@eswincomputing.com>

From: Shen Peiting <shenpeiting@eswincomputing.com>

Scalar calculating float sum_square optimized by using RVV instructions

Benchmarks on Spike(cycles):
len=128
ac3_sum_square_butterfly_float_c: 7986
ac3_sum_square_butterfly_float_rvv: 146
len=1280
ac3_sum_square_butterfly_float_c: 79410
ac3_sum_square_butterfly_float_rvv: 1154

Co-Authored by: Yang Xiaojun <yangxiaojun@eswincomputing.com>
Co-Authored by: Huang Xing <huangxing1@eswincomputing.com>
Co-Authored by: Zeng Fanchen <zengfanchen@eswincomputing.com>
Signed-off-by: Shen Peiting <shenpeiting@eswincomputing.com>
---
 libavcodec/riscv/ac3dsp_init.c |  6 ++++
 libavcodec/riscv/ac3dsp_rvv.S  | 54 ++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/libavcodec/riscv/ac3dsp_init.c b/libavcodec/riscv/ac3dsp_init.c
index 4fd4abe83e..d3aa20623a 100644
--- a/libavcodec/riscv/ac3dsp_init.c
+++ b/libavcodec/riscv/ac3dsp_init.c
@@ -30,6 +30,10 @@ void ff_ac3_sum_square_butterfly_int32_rvv(int64_t sum[4],
                                             const int32_t *coef0,
                                             const int32_t *coef1,
                                             int len);
+void ff_ac3_sum_square_butterfly_float_rvv(float sum[4],
+                                            const float *coef0,
+                                            const float *coef1,
+                                            int len);
 
 av_cold void ff_ac3dsp_init_riscv(AC3DSPContext *c)
 {
@@ -39,6 +43,8 @@ av_cold void ff_ac3dsp_init_riscv(AC3DSPContext *c)
         c->ac3_exponent_min = ff_ac3_exponent_min_rvv;
         c->float_to_fixed24 = ff_float_to_fixed24_rvv;
     }
+    if (flags & AV_CPU_FLAG_RVV_F32)
+        c->sum_square_butterfly_float = ff_ac3_sum_square_butterfly_float_rvv;
 #if (__riscv_xlen >= 64)
     if (flags & AV_CPU_FLAG_RVV_I64)
         c->sum_square_butterfly_int32 = ff_ac3_sum_square_butterfly_int32_rvv;
diff --git a/libavcodec/riscv/ac3dsp_rvv.S b/libavcodec/riscv/ac3dsp_rvv.S
index 4e0d238f85..05a4d44938 100644
--- a/libavcodec/riscv/ac3dsp_rvv.S
+++ b/libavcodec/riscv/ac3dsp_rvv.S
@@ -116,3 +116,57 @@ func ff_ac3_sum_square_butterfly_int32_rvv, zve64x
     addi            a0, a0, 8
     ret
 endfunc
+
+
+func ff_ac3_sum_square_butterfly_float_rvv, zve32f
+    #Round Up
+    li              t1, 0x61
+    fscsr           t1
+    vsetvli         t0, a3, e32, m4
+    vle32.v         v0, (a1)
+    vle32.v         v4, (a2)
+    vfadd.vv        v8, v0, v4
+    vfsub.vv        v12, v0, v4
+    vfmul.vv        v16, v0, v0
+    vfmul.vv        v20, v4, v4
+    vfmul.vv        v24, v8, v8
+    vfmul.vv        v28, v12, v12
+    sub             a3, a3, t0
+    slli            t0, t0, 2
+    add             a1, a1, t0
+    add             a2, a2, t0
+    beq             a3, x0, 2f
+1:
+    vsetvli         t0, a3, e32, m4
+    vle32.v         v0, (a1)
+    vle32.v         v4, (a2)
+    vfadd.vv        v8, v0, v4
+    vfsub.vv        v12, v0, v4
+    vfmacc.vv       v16, v0, v0
+    vfmacc.vv       v20, v4, v4
+    vfmacc.vv       v24, v8, v8
+    vfmacc.vv       v28, v12, v12
+    sub             a3, a3, t0
+    slli            t0, t0, 2
+    add             a1, a1, t0
+    add             a2, a2, t0
+    bnez            a3, 1b
+2:
+    vsetvli         t0, x0, e32, m4
+    fcvt.s.w        f0, x0
+    vfmv.v.f        v0, f0
+    vfredsum.vs     v0, v16, v0
+    vfredsum.vs     v1, v20, v1
+    vfredsum.vs     v2, v24, v2
+    vfredsum.vs     v3, v28, v3
+    vsetivli        t0, 1, e32, m1
+    vse32.v         v0, (a0)
+    addi            a0, a0, 4
+    vse32.v         v1, (a0)
+    addi            a0, a0, 4
+    vse32.v         v2, (a0)
+    addi            a0, a0, 4
+    vse32.v         v3, (a0)
+    addi            a0, a0, 4
+    ret
+endfunc
-- 
2.17.1

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  parent reply	other threads:[~2023-06-15 10:37 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-15 10:36 [FFmpeg-devel] [PATCH 0/6] RISC-V initial ac3dsp Peiting Shen
2023-06-15 10:36 ` [FFmpeg-devel] [PATCH 1/6] lavc/ac3dsp: RISC-V V ac3_exponent_min Peiting Shen
2023-06-15 18:02   ` Rémi Denis-Courmont
2023-06-15 10:36 ` [FFmpeg-devel] [PATCH 2/6] lavc/ac3dsp: RISC-V V float_to_fixed24 Peiting Shen
2023-06-15 18:06   ` Rémi Denis-Courmont
2023-06-15 10:36 ` [FFmpeg-devel] [PATCH 3/6] lavc/ac3dsp: RISC-V V ac3_sum_square_butterfly_int32 Peiting Shen
2023-06-15 19:25   ` Rémi Denis-Courmont
2023-06-16 10:15     ` 沈佩婷
2023-06-15 10:36 ` Peiting Shen [this message]
2023-06-15 10:36 ` [FFmpeg-devel] [PATCH 5/6] lavc/ac3dsp: RISC-V V ac3_compute_mantissa_size Peiting Shen
2023-06-15 10:36 ` [FFmpeg-devel] [PATCH 6/6] lavc/ac3dsp: RISC-V B ac3_extract_exponents Peiting Shen
2023-06-15 19:18   ` Rémi Denis-Courmont
2023-06-15 13:57 ` [FFmpeg-devel] [PATCH 0/6] RISC-V initial ac3dsp Lynne
2023-06-15 19:10   ` Rémi Denis-Courmont

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