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* [FFmpeg-devel] [PATCHv2 0/6] RISC-V CPU extensions
@ 2022-09-17 12:45 Rémi Denis-Courmont
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 1/6] lavu/cpu: detect RISC-V base extensions remi
                   ` (5 more replies)
  0 siblings, 6 replies; 7+ messages in thread
From: Rémi Denis-Courmont @ 2022-09-17 12:45 UTC (permalink / raw)
  To: ffmpeg-devel

	Hi,

This adds configure, compile-time, run-time detection for RISC-V scalar
and vector extensions. Also a couple of scalar optimisations.

----------------------------------------------------------------
Rémi Denis-Courmont (6):
      lavu/cpu: detect RISC-V base extensions
      lavu/cpu: CPU flags for the RISC-V Vector extension
      configure: probe RISC-V Vector extension
      lavu/riscv: initial common header for assembler macros
      lavc/audiodsp: add RISC-V F float vector clip
      lavc/pixblockdsp: RISC-V scalar optimisations

 Makefile                            |   2 +-
 configure                           |  15 +++++
 ffbuild/arch.mak                    |   2 +
 libavcodec/audiodsp.c               |   2 +
 libavcodec/audiodsp.h               |   1 +
 libavcodec/pixblockdsp.c            |   2 +
 libavcodec/pixblockdsp.h            |   2 +
 libavcodec/riscv/Makefile           |   4 ++
 libavcodec/riscv/audiodsp_init.c    |  31 +++++++++++
 libavcodec/riscv/audiodsp_rvf.S     |  46 +++++++++++++++
 libavcodec/riscv/pixblockdsp_init.c |  43 ++++++++++++++
 libavcodec/riscv/pixblockdsp_rvi.S  |  57 +++++++++++++++++++
 libavutil/cpu.c                     |  13 +++++
 libavutil/cpu.h                     |   9 +++
 libavutil/cpu_internal.h            |   3 +
 libavutil/riscv/Makefile            |   1 +
 libavutil/riscv/asm.S               |  74 ++++++++++++++++++++++++
 libavutil/riscv/cpu.c               | 108 ++++++++++++++++++++++++++++++++++++
 tests/checkasm/checkasm.c           |   8 +++
 19 files changed, 422 insertions(+), 1 deletion(-)
 create mode 100644 libavcodec/riscv/Makefile
 create mode 100644 libavcodec/riscv/audiodsp_init.c
 create mode 100644 libavcodec/riscv/audiodsp_rvf.S
 create mode 100644 libavcodec/riscv/pixblockdsp_init.c
 create mode 100644 libavcodec/riscv/pixblockdsp_rvi.S
 create mode 100644 libavutil/riscv/Makefile
 create mode 100644 libavutil/riscv/asm.S
 create mode 100644 libavutil/riscv/cpu.c

-- 
Rémi Denis-Courmont
http://www.remlab.net/



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^ permalink raw reply	[flat|nested] 7+ messages in thread
* [FFmpeg-devel] [PATCH 1/6] lavu/cpu: detect RISC-V base extensions
  2022-09-17 12:45 [FFmpeg-devel] [PATCHv2 0/6] RISC-V CPU extensions Rémi Denis-Courmont
@ 2022-09-17 12:45 ` remi
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 2/6] lavu/cpu: CPU flags for the RISC-V Vector extension remi
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: remi @ 2022-09-17 12:45 UTC (permalink / raw)
  To: ffmpeg-devel

From: Rémi Denis-Courmont <remi@remlab.net>

This introduces compile-time and run-time CPU detection on RISC-V. In
practice, I doubt that FFmpeg will ever see a RISC-V CPU without all of
I, F and D extensions, and if it does, it probably won't have run-time
detection. So the flags are essentially always set.

But as things stand, checkasm wants them that way. Compare the ARMV8
flag on AArch64. We are nowhere near running short on CPU flag bits.
---
 libavutil/cpu.c           |  9 ++++++
 libavutil/cpu.h           |  5 +++
 libavutil/cpu_internal.h  |  3 ++
 libavutil/riscv/Makefile  |  1 +
 libavutil/riscv/cpu.c     | 64 +++++++++++++++++++++++++++++++++++++++
 tests/checkasm/checkasm.c |  4 +++
 6 files changed, 86 insertions(+)
 create mode 100644 libavutil/riscv/Makefile
 create mode 100644 libavutil/riscv/cpu.c

diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index 0035e927a5..78e92a1bf6 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -62,6 +62,8 @@ static int get_cpu_flags(void)
     return ff_get_cpu_flags_arm();
 #elif ARCH_PPC
     return ff_get_cpu_flags_ppc();
+#elif ARCH_RISCV
+    return ff_get_cpu_flags_riscv();
 #elif ARCH_X86
     return ff_get_cpu_flags_x86();
 #elif ARCH_LOONGARCH
@@ -95,6 +97,9 @@ void av_force_cpu_flags(int arg){
         arg |= AV_CPU_FLAG_MMX;
     }
 
+#if ARCH_RISCV
+    arg = ff_force_cpu_flags_riscv(arg);
+#endif
     atomic_store_explicit(&cpu_flags, arg, memory_order_relaxed);
 }
 
@@ -178,6 +183,10 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
 #elif ARCH_LOONGARCH
         { "lsx",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LSX      },    .unit = "flags" },
         { "lasx",     NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LASX     },    .unit = "flags" },
+#elif ARCH_RISCV
+        { "rvi",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVI      },    .unit = "flags" },
+        { "rvf",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVF      },    .unit = "flags" },
+        { "rvd",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVD      },    .unit = "flags" },
 #endif
         { NULL },
     };
diff --git a/libavutil/cpu.h b/libavutil/cpu.h
index 9711e574c5..9aae2ccc7a 100644
--- a/libavutil/cpu.h
+++ b/libavutil/cpu.h
@@ -78,6 +78,11 @@
 #define AV_CPU_FLAG_LSX          (1 << 0)
 #define AV_CPU_FLAG_LASX         (1 << 1)
 
+// RISC-V extensions
+#define AV_CPU_FLAG_RVI          (1 << 0) ///< I (full GPR bank)
+#define AV_CPU_FLAG_RVF          (1 << 1) ///< F (single precision FP)
+#define AV_CPU_FLAG_RVD          (1 << 2) ///< D (double precision FP)
+
 /**
  * Return the flags which specify extensions supported by the CPU.
  * The returned value is affected by av_force_cpu_flags() if that was used
diff --git a/libavutil/cpu_internal.h b/libavutil/cpu_internal.h
index 650d47fc96..9ddf11488b 100644
--- a/libavutil/cpu_internal.h
+++ b/libavutil/cpu_internal.h
@@ -48,9 +48,12 @@ int ff_get_cpu_flags_mips(void);
 int ff_get_cpu_flags_aarch64(void);
 int ff_get_cpu_flags_arm(void);
 int ff_get_cpu_flags_ppc(void);
+int ff_get_cpu_flags_riscv(void);
 int ff_get_cpu_flags_x86(void);
 int ff_get_cpu_flags_loongarch(void);
 
+int ff_force_cpu_flags_riscv(int flags);
+
 size_t ff_get_cpu_max_align_mips(void);
 size_t ff_get_cpu_max_align_aarch64(void);
 size_t ff_get_cpu_max_align_arm(void);
diff --git a/libavutil/riscv/Makefile b/libavutil/riscv/Makefile
new file mode 100644
index 0000000000..1f818043dc
--- /dev/null
+++ b/libavutil/riscv/Makefile
@@ -0,0 +1 @@
+OBJS += riscv/cpu.o
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
new file mode 100644
index 0000000000..b382e8fa07
--- /dev/null
+++ b/libavutil/riscv/cpu.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "libavutil/cpu.h"
+#include "libavutil/cpu_internal.h"
+#include "libavutil/log.h"
+#include "config.h"
+
+#if HAVE_GETAUXVAL
+#include <sys/auxv.h>
+#define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
+#endif
+
+int ff_force_cpu_flags_riscv(int flags)
+{
+    if ((flags & AV_CPU_FLAG_RVD) && !(flags & AV_CPU_FLAG_RVF)) {
+        av_log(NULL, AV_LOG_WARNING, "RV%s implied by specified flags\n", "F");
+        flags |= AV_CPU_FLAG_RVF;
+    }
+
+    return flags;
+}
+
+int ff_get_cpu_flags_riscv(void)
+{
+    int ret = 0;
+#if HAVE_GETAUXVAL
+    const unsigned long hwcap = getauxval(AT_HWCAP);
+
+    if (hwcap & HWCAP_RV('I'))
+        ret |= AV_CPU_FLAG_RVI;
+    if (hwcap & HWCAP_RV('F'))
+        ret |= AV_CPU_FLAG_RVF;
+    if (hwcap & HWCAP_RV('D'))
+        ret |= AV_CPU_FLAG_RVD;
+#endif
+
+#ifdef __riscv_i
+    ret |= AV_CPU_FLAG_RVI;
+#endif
+#if defined (__riscv_flen) && (__riscv_flen >= 32)
+    ret |= AV_CPU_FLAG_RVF;
+#if (__riscv_flen >= 64)
+    ret |= AV_CPU_FLAG_RVD;
+#endif
+#endif
+
+    return ret;
+}
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c
index e56fd3850e..ea25fbad75 100644
--- a/tests/checkasm/checkasm.c
+++ b/tests/checkasm/checkasm.c
@@ -226,6 +226,10 @@ static const struct {
     { "ALTIVEC",  "altivec",  AV_CPU_FLAG_ALTIVEC },
     { "VSX",      "vsx",      AV_CPU_FLAG_VSX },
     { "POWER8",   "power8",   AV_CPU_FLAG_POWER8 },
+#elif ARCH_RISCV
+    { "RVI",      "rvi",      AV_CPU_FLAG_RVI },
+    { "RVF",      "rvf",      AV_CPU_FLAG_RVF },
+    { "RVD",      "rvd",      AV_CPU_FLAG_RVD },
 #elif ARCH_MIPS
     { "MMI",      "mmi",      AV_CPU_FLAG_MMI },
     { "MSA",      "msa",      AV_CPU_FLAG_MSA },
-- 
2.37.2

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^ permalink raw reply	[flat|nested] 7+ messages in thread
* [FFmpeg-devel] [PATCH 2/6] lavu/cpu: CPU flags for the RISC-V Vector extension
  2022-09-17 12:45 [FFmpeg-devel] [PATCHv2 0/6] RISC-V CPU extensions Rémi Denis-Courmont
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 1/6] lavu/cpu: detect RISC-V base extensions remi
@ 2022-09-17 12:45 ` remi
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 3/6] configure: probe " remi
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: remi @ 2022-09-17 12:45 UTC (permalink / raw)
  To: ffmpeg-devel

From: Rémi Denis-Courmont <remi@remlab.net>

RVV defines a total of 12 different extensions, including:

- 5 different instruction subsets:
  - Zve32x: 8-, 16- and 32-bit integers,
  - Zve32f: Zve32x plus single precision floats,
  - Zve64x: Zve32x plus 64-bit integers,
  - Zve64f: Zve32f plus Zve64x,
  - Zve64d: Zve64f plus double precision floats.

- 6 different vector lengths:
  - Zvl32b (embedded only),
  - Zvl64b (embedded only),
  - Zvl128b,
  - Zvl256b,
  - Zvl512b,
  - Zvl1024b,

- and the V extension proper: equivalent to Zve64f and Zvl128b.

In total, there are 6 different possible sets of supported instructions
(including the empty set), but for convenience we allocate one bit for
each type sets: up-to-32-bit ints (ZVE32X), floats (ZV32F),
64-bit ints (ZV64X) and doubles (ZVE64D).

Whence the vector size is needed, it can be retrieved by reading the
unprivileged read-only vlenb CSR. This should probably be a separate
helper macro if needed at a later point.
---
 libavutil/cpu.c           |  4 ++++
 libavutil/cpu.h           |  4 ++++
 libavutil/riscv/cpu.c     | 46 ++++++++++++++++++++++++++++++++++++++-
 tests/checkasm/checkasm.c | 10 ++++++---
 4 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index 78e92a1bf6..58ae4858b4 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -187,6 +187,10 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
         { "rvi",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVI      },    .unit = "flags" },
         { "rvf",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVF      },    .unit = "flags" },
         { "rvd",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVD      },    .unit = "flags" },
+        { "rvve32",   NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVE32X},    .unit = "flags" },
+        { "rvvf",     NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVE32F},    .unit = "flags" },
+        { "rvve64",   NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVE64X},    .unit = "flags" },
+        { "rvv",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVE64D},    .unit = "flags" },
 #endif
         { NULL },
     };
diff --git a/libavutil/cpu.h b/libavutil/cpu.h
index 9aae2ccc7a..00698e30ef 100644
--- a/libavutil/cpu.h
+++ b/libavutil/cpu.h
@@ -82,6 +82,10 @@
 #define AV_CPU_FLAG_RVI          (1 << 0) ///< I (full GPR bank)
 #define AV_CPU_FLAG_RVF          (1 << 1) ///< F (single precision FP)
 #define AV_CPU_FLAG_RVD          (1 << 2) ///< D (double precision FP)
+#define AV_CPU_FLAG_RV_ZVE32X    (1 << 3) ///< Vectors of 8/16/32-bit int's */
+#define AV_CPU_FLAG_RV_ZVE32F    (1 << 4) ///< Vectors of float's */
+#define AV_CPU_FLAG_RV_ZVE64X    (1 << 5) ///< Vectors of 64-bit int's */
+#define AV_CPU_FLAG_RV_ZVE64D    (1 << 6) ///< Vectors of double's
 
 /**
  * Return the flags which specify extensions supported by the CPU.
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
index b382e8fa07..3e6c99819b 100644
--- a/libavutil/riscv/cpu.c
+++ b/libavutil/riscv/cpu.c
@@ -28,7 +28,32 @@
 
 int ff_force_cpu_flags_riscv(int flags)
 {
-    if ((flags & AV_CPU_FLAG_RVD) && !(flags & AV_CPU_FLAG_RVF)) {
+    if ((flags & AV_CPU_FLAG_RV_ZVE64D) && !(flags & AV_CPU_FLAG_RV_ZVE64X)) {
+        av_log(NULL, AV_LOG_WARNING, "RV%s implied by specified flags\n",
+               "_ZVE64X");
+        flags |= AV_CPU_FLAG_RV_ZVE64X;
+    }
+
+    if ((flags & AV_CPU_FLAG_RV_ZVE64D) && !(flags & AV_CPU_FLAG_RV_ZVE32F)) {
+        av_log(NULL, AV_LOG_WARNING, "RV%s implied by specified flags\n",
+               "_ZVE32F");
+        flags |= AV_CPU_FLAG_RV_ZVE32F;
+    }
+
+    if ((flags & (AV_CPU_FLAG_RV_ZVE64X | AV_CPU_FLAG_RV_ZVE32F))
+        && !(flags & AV_CPU_FLAG_RV_ZVE32X)) {
+        av_log(NULL, AV_LOG_WARNING, "RV%s implied by specified flags\n",
+               "_ZVE32X");
+        flags |= AV_CPU_FLAG_RV_ZVE32X;
+    }
+
+    if ((flags & AV_CPU_FLAG_RV_ZVE64D) && !(flags & AV_CPU_FLAG_RVD)) {
+        av_log(NULL, AV_LOG_WARNING, "RV%s implied by specified flags\n", "D");
+        flags |= AV_CPU_FLAG_RVD;
+    }
+
+    if ((flags & (AV_CPU_FLAG_RVD | AV_CPU_FLAG_RV_ZVE32F))
+        && !(flags & AV_CPU_FLAG_RVF)) {
         av_log(NULL, AV_LOG_WARNING, "RV%s implied by specified flags\n", "F");
         flags |= AV_CPU_FLAG_RVF;
     }
@@ -48,6 +73,11 @@ int ff_get_cpu_flags_riscv(void)
         ret |= AV_CPU_FLAG_RVF;
     if (hwcap & HWCAP_RV('D'))
         ret |= AV_CPU_FLAG_RVD;
+
+    /* The V extension implies all Zve* functional subsets */
+    if (hwcap & HWCAP_RV('V'))
+        ret |= AV_CPU_FLAG_RV_ZVE32X | AV_CPU_FLAG_RV_ZVE64X
+             | AV_CPU_FLAG_RV_ZVE32F | AV_CPU_FLAG_RV_ZVE64D;
 #endif
 
 #ifdef __riscv_i
@@ -58,6 +88,20 @@ int ff_get_cpu_flags_riscv(void)
 #if (__riscv_flen >= 64)
     ret |= AV_CPU_FLAG_RVD;
 #endif
+#endif
+
+    /* If RV-V is enabled statically at compile-time, check the details. */
+#ifdef __riscv_vectors
+    ret |= AV_CPU_FLAG_RV_ZVE32X;
+#if __riscv_v_elen >= 64
+    ret |= AV_CPU_FLAG_RV_ZVE64X;
+#endif
+#if __riscv_v_elen_fp >= 32
+    ret |= AV_CPU_FLAG_RV_ZVE32F;
+#if __riscv_v_elen_fp >= 64
+    ret |= AV_CPU_FLAG_RV_ZVE64F;
+#endif
+#endif
 #endif
 
     return ret;
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c
index ea25fbad75..2f863c9a8a 100644
--- a/tests/checkasm/checkasm.c
+++ b/tests/checkasm/checkasm.c
@@ -227,9 +227,13 @@ static const struct {
     { "VSX",      "vsx",      AV_CPU_FLAG_VSX },
     { "POWER8",   "power8",   AV_CPU_FLAG_POWER8 },
 #elif ARCH_RISCV
-    { "RVI",      "rvi",      AV_CPU_FLAG_RVI },
-    { "RVF",      "rvf",      AV_CPU_FLAG_RVF },
-    { "RVD",      "rvd",      AV_CPU_FLAG_RVD },
+    { "RVI",        "rvi",       AV_CPU_FLAG_RVI },
+    { "RVF",        "rvf",       AV_CPU_FLAG_RVF },
+    { "RVD",        "rvd",       AV_CPU_FLAG_RVD },
+    { "RV_Zve32x",  "rv_zve32x", AV_CPU_FLAG_RV_ZVE32X },
+    { "RV_Zve32f",  "rv_zve32f", AV_CPU_FLAG_RV_ZVE32F },
+    { "RV_Zve64x",  "rv_zve64x", AV_CPU_FLAG_RV_ZVE64X },
+    { "RV_Zve64d",  "rv_zve64d", AV_CPU_FLAG_RV_ZVE64D },
 #elif ARCH_MIPS
     { "MMI",      "mmi",      AV_CPU_FLAG_MMI },
     { "MSA",      "msa",      AV_CPU_FLAG_MSA },
-- 
2.37.2

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^ permalink raw reply	[flat|nested] 7+ messages in thread
* [FFmpeg-devel] [PATCH 3/6] configure: probe RISC-V Vector extension
  2022-09-17 12:45 [FFmpeg-devel] [PATCHv2 0/6] RISC-V CPU extensions Rémi Denis-Courmont
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 1/6] lavu/cpu: detect RISC-V base extensions remi
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 2/6] lavu/cpu: CPU flags for the RISC-V Vector extension remi
@ 2022-09-17 12:45 ` remi
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 4/6] lavu/riscv: initial common header for assembler macros remi
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: remi @ 2022-09-17 12:45 UTC (permalink / raw)
  To: ffmpeg-devel

From: Rémi Denis-Courmont <remi@remlab.net>

---
 Makefile         |  2 +-
 configure        | 15 +++++++++++++++
 ffbuild/arch.mak |  2 ++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 61f79e27ae..1fb742f390 100644
--- a/Makefile
+++ b/Makefile
@@ -91,7 +91,7 @@ ffbuild/.config: $(CONFIGURABLE_COMPONENTS)
 SUBDIR_VARS := CLEANFILES FFLIBS HOSTPROGS TESTPROGS TOOLS               \
                HEADERS ARCH_HEADERS BUILT_HEADERS SKIPHEADERS            \
                ARMV5TE-OBJS ARMV6-OBJS ARMV8-OBJS VFP-OBJS NEON-OBJS     \
-               ALTIVEC-OBJS VSX-OBJS MMX-OBJS X86ASM-OBJS                \
+               ALTIVEC-OBJS VSX-OBJS RVV-OBJS MMX-OBJS X86ASM-OBJS       \
                MIPSFPU-OBJS MIPSDSPR2-OBJS MIPSDSP-OBJS MSA-OBJS         \
                MMI-OBJS LSX-OBJS LASX-OBJS OBJS SLIBOBJS SHLIBOBJS       \
                STLIBOBJS HOSTOBJS TESTOBJS
diff --git a/configure b/configure
index 240ae942d1..32be5ad625 100755
--- a/configure
+++ b/configure
@@ -462,6 +462,7 @@ Optimization options (experts only):
   --disable-mmi            disable Loongson MMI optimizations
   --disable-lsx            disable Loongson LSX optimizations
   --disable-lasx           disable Loongson LASX optimizations
+  --disable-rvv            disable RISC-V Vector optimizations
   --disable-fast-unaligned consider unaligned accesses slow
 
 Developer options (useful when working on FFmpeg itself):
@@ -2126,6 +2127,10 @@ ARCH_EXT_LIST_PPC="
     vsx
 "
 
+ARCH_EXT_LIST_RISCV="
+    rvv
+"
+
 ARCH_EXT_LIST_X86="
     $ARCH_EXT_LIST_X86_SIMD
     cpunop
@@ -2135,6 +2140,7 @@ ARCH_EXT_LIST_X86="
 ARCH_EXT_LIST="
     $ARCH_EXT_LIST_ARM
     $ARCH_EXT_LIST_PPC
+    $ARCH_EXT_LIST_RISCV
     $ARCH_EXT_LIST_X86
     $ARCH_EXT_LIST_MIPS
     $ARCH_EXT_LIST_LOONGSON
@@ -2642,6 +2648,8 @@ ppc4xx_deps="ppc"
 vsx_deps="altivec"
 power8_deps="vsx"
 
+rvv_deps="riscv"
+
 loongson2_deps="mips"
 loongson3_deps="mips"
 mmi_deps_any="loongson2 loongson3"
@@ -6112,6 +6120,10 @@ elif enabled ppc; then
         check_cpp_condition power8 "altivec.h" "defined(_ARCH_PWR8)"
     fi
 
+elif enabled riscv; then
+
+    enabled rvv && check_inline_asm rvv '".option arch, +v\nvsetivli zero, 0, e8, m1, ta, ma"'
+
 elif enabled x86; then
 
     check_builtin rdtsc    intrin.h   "__rdtsc()"
@@ -7598,6 +7610,9 @@ if enabled loongarch; then
     echo "LSX enabled               ${lsx-no}"
     echo "LASX enabled              ${lasx-no}"
 fi
+if enabled riscv; then
+    echo "RISC-V Vector enabled     ${riscv-no}"
+fi
 echo "debug symbols             ${debug-no}"
 echo "strip symbols             ${stripping-no}"
 echo "optimize for size         ${small-no}"
diff --git a/ffbuild/arch.mak b/ffbuild/arch.mak
index 997e31e85e..39d76ee152 100644
--- a/ffbuild/arch.mak
+++ b/ffbuild/arch.mak
@@ -15,5 +15,7 @@ OBJS-$(HAVE_LASX)      += $(LASX-OBJS)       $(LASX-OBJS-yes)
 OBJS-$(HAVE_ALTIVEC) += $(ALTIVEC-OBJS) $(ALTIVEC-OBJS-yes)
 OBJS-$(HAVE_VSX)     += $(VSX-OBJS) $(VSX-OBJS-yes)
 
+OBJS-$(HAVE_RVV)     += $(RVV-OBJS)     $(RVV-OBJS-yes)
+
 OBJS-$(HAVE_MMX)     += $(MMX-OBJS)     $(MMX-OBJS-yes)
 OBJS-$(HAVE_X86ASM)  += $(X86ASM-OBJS)  $(X86ASM-OBJS-yes)
-- 
2.37.2

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^ permalink raw reply	[flat|nested] 7+ messages in thread
* [FFmpeg-devel] [PATCH 4/6] lavu/riscv: initial common header for assembler macros
  2022-09-17 12:45 [FFmpeg-devel] [PATCHv2 0/6] RISC-V CPU extensions Rémi Denis-Courmont
                   ` (2 preceding siblings ...)
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 3/6] configure: probe " remi
@ 2022-09-17 12:45 ` remi
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 5/6] lavc/audiodsp: add RISC-V F float vector clip remi
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 6/6] lavc/pixblockdsp: RISC-V scalar optimisations remi
  5 siblings, 0 replies; 7+ messages in thread
From: remi @ 2022-09-17 12:45 UTC (permalink / raw)
  To: ffmpeg-devel

From: Rémi Denis-Courmont <remi@remlab.net>

---
 libavutil/riscv/asm.S | 74 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 libavutil/riscv/asm.S

diff --git a/libavutil/riscv/asm.S b/libavutil/riscv/asm.S
new file mode 100644
index 0000000000..7623c161cf
--- /dev/null
+++ b/libavutil/riscv/asm.S
@@ -0,0 +1,74 @@
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "config.h"
+
+#if defined (__riscv_float_abi_soft)
+#define NOHWF
+#define NOHWD
+#define HWF   #
+#define HWD   #
+#elif defined (__riscv_float_abi_single)
+#define NOHWF #
+#define NOHWD
+#define HWF
+#define HWD   #
+#else
+#define NOHWF #
+#define NOHWD #
+#define HWF
+#define HWD
+#endif
+
+        .macro func sym, ext=
+            .text
+            .align 2
+
+            .option push
+            .ifnb \ext
+            .option arch, +\ext
+            .endif
+
+            .global \sym
+            .hidden \sym
+            .type   \sym, %function
+            \sym:
+
+            .macro endfunc
+                .size   \sym, . - \sym
+                .option pop
+                .previous
+                .purgem endfunc
+            .endm
+        .endm
+
+        .macro const sym, align=3, relocate=0
+            .if \relocate
+                .pushsection .data.rel.ro
+            .else
+                .pushsection .rodata
+            .endif
+            .align \align
+            \sym:
+
+            .macro endconst
+                .size  \sym, . - \sym
+                .popsection
+                .purgem endconst
+            .endm
+        .endm
-- 
2.37.2

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^ permalink raw reply	[flat|nested] 7+ messages in thread
* [FFmpeg-devel] [PATCH 5/6] lavc/audiodsp: add RISC-V F float vector clip
  2022-09-17 12:45 [FFmpeg-devel] [PATCHv2 0/6] RISC-V CPU extensions Rémi Denis-Courmont
                   ` (3 preceding siblings ...)
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 4/6] lavu/riscv: initial common header for assembler macros remi
@ 2022-09-17 12:45 ` remi
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 6/6] lavc/pixblockdsp: RISC-V scalar optimisations remi
  5 siblings, 0 replies; 7+ messages in thread
From: remi @ 2022-09-17 12:45 UTC (permalink / raw)
  To: ffmpeg-devel

From: Rémi Denis-Courmont <remi@remlab.net>

RV64G supports MIN & MAX instructions natively only on floating point
registers, not general purpose ones. The later would require the Zbb
extension. Due to that, it is actually faster to perform the clipping
"properly" in FPU.

Benchmarked on SiFive U74-MC:

audiodsp.vector_clipf_c: 29551.5
audiodsp.vector_clipf_rvf: 17871.0

Also tried unrolling with 2 or 8 elements but it gets worse either way.
---
 libavcodec/audiodsp.c            |  2 ++
 libavcodec/audiodsp.h            |  1 +
 libavcodec/riscv/Makefile        |  2 ++
 libavcodec/riscv/audiodsp_init.c | 31 +++++++++++++++++++++
 libavcodec/riscv/audiodsp_rvf.S  | 46 ++++++++++++++++++++++++++++++++
 5 files changed, 82 insertions(+)
 create mode 100644 libavcodec/riscv/Makefile
 create mode 100644 libavcodec/riscv/audiodsp_init.c
 create mode 100644 libavcodec/riscv/audiodsp_rvf.S

diff --git a/libavcodec/audiodsp.c b/libavcodec/audiodsp.c
index ff43e87dce..eba6e809fd 100644
--- a/libavcodec/audiodsp.c
+++ b/libavcodec/audiodsp.c
@@ -113,6 +113,8 @@ av_cold void ff_audiodsp_init(AudioDSPContext *c)
     ff_audiodsp_init_arm(c);
 #elif ARCH_PPC
     ff_audiodsp_init_ppc(c);
+#elif ARCH_RISCV
+    ff_audiodsp_init_riscv(c);
 #elif ARCH_X86
     ff_audiodsp_init_x86(c);
 #endif
diff --git a/libavcodec/audiodsp.h b/libavcodec/audiodsp.h
index aa6fa7898b..485b512839 100644
--- a/libavcodec/audiodsp.h
+++ b/libavcodec/audiodsp.h
@@ -55,6 +55,7 @@ typedef struct AudioDSPContext {
 void ff_audiodsp_init(AudioDSPContext *c);
 void ff_audiodsp_init_arm(AudioDSPContext *c);
 void ff_audiodsp_init_ppc(AudioDSPContext *c);
+void ff_audiodsp_init_riscv(AudioDSPContext *c);
 void ff_audiodsp_init_x86(AudioDSPContext *c);
 
 #endif /* AVCODEC_AUDIODSP_H */
diff --git a/libavcodec/riscv/Makefile b/libavcodec/riscv/Makefile
new file mode 100644
index 0000000000..414a9e9bd8
--- /dev/null
+++ b/libavcodec/riscv/Makefile
@@ -0,0 +1,2 @@
+OBJS-$(CONFIG_AUDIODSP) += riscv/audiodsp_init.o \
+                           riscv/audiodsp_rvf.o
diff --git a/libavcodec/riscv/audiodsp_init.c b/libavcodec/riscv/audiodsp_init.c
new file mode 100644
index 0000000000..ebd008a311
--- /dev/null
+++ b/libavcodec/riscv/audiodsp_init.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "libavutil/attributes.h"
+#include "libavutil/cpu.h"
+#include "libavcodec/audiodsp.h"
+
+void ff_vector_clipf_rvf(float *dst, const float *src, int len, float min, float max);
+
+av_cold void ff_audiodsp_init_riscv(AudioDSPContext *c)
+{
+    int flags = av_get_cpu_flags();
+
+    if (flags & AV_CPU_FLAG_RVF)
+        c->vector_clipf = ff_vector_clipf_rvf;
+}
diff --git a/libavcodec/riscv/audiodsp_rvf.S b/libavcodec/riscv/audiodsp_rvf.S
new file mode 100644
index 0000000000..d2c042bb26
--- /dev/null
+++ b/libavcodec/riscv/audiodsp_rvf.S
@@ -0,0 +1,46 @@
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "libavutil/riscv/asm.S"
+
+func ff_vector_clipf_rvf, f
+NOHWF   fmv.w.x fa0, a3
+NOHWF   fmv.w.x fa1, a4
+1:
+        flw     ft0,   (a1)
+        flw     ft1,  4(a1)
+        fmax.s  ft0, ft0, fa0
+        flw     ft2,  8(a1)
+        fmax.s  ft1, ft1, fa0
+        flw     ft3, 12(a1)
+        fmax.s  ft2, ft2, fa0
+        addi    a2, a2, -4
+        fmax.s  ft3, ft3, fa0
+        addi    a1, a1, 16
+        fmin.s  ft0, ft0, fa1
+        fmin.s  ft1, ft1, fa1
+        fsw     ft0,   (a0)
+        fmin.s  ft2, ft2, fa1
+        fsw     ft1,  4(a0)
+        fmin.s  ft3, ft3, fa1
+        fsw     ft2,  8(a0)
+        fsw     ft3, 12(a0)
+        addi    a0, a0, 16
+        bnez    a2, 1b
+        ret
+endfunc
-- 
2.37.2

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^ permalink raw reply	[flat|nested] 7+ messages in thread
* [FFmpeg-devel] [PATCH 6/6] lavc/pixblockdsp: RISC-V scalar optimisations
  2022-09-17 12:45 [FFmpeg-devel] [PATCHv2 0/6] RISC-V CPU extensions Rémi Denis-Courmont
                   ` (4 preceding siblings ...)
  2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 5/6] lavc/audiodsp: add RISC-V F float vector clip remi
@ 2022-09-17 12:45 ` remi
  5 siblings, 0 replies; 7+ messages in thread
From: remi @ 2022-09-17 12:45 UTC (permalink / raw)
  To: ffmpeg-devel

From: Rémi Denis-Courmont <remi@remlab.net>

Benchmarks:
get_pixels_c: 180.0
get_pixels_rvi: 136.7
---
 libavcodec/pixblockdsp.c            |  2 +
 libavcodec/pixblockdsp.h            |  2 +
 libavcodec/riscv/Makefile           |  2 +
 libavcodec/riscv/pixblockdsp_init.c | 43 ++++++++++++++++++++++
 libavcodec/riscv/pixblockdsp_rvi.S  | 57 +++++++++++++++++++++++++++++
 5 files changed, 106 insertions(+)
 create mode 100644 libavcodec/riscv/pixblockdsp_init.c
 create mode 100644 libavcodec/riscv/pixblockdsp_rvi.S

diff --git a/libavcodec/pixblockdsp.c b/libavcodec/pixblockdsp.c
index 17c487da1e..4294075cee 100644
--- a/libavcodec/pixblockdsp.c
+++ b/libavcodec/pixblockdsp.c
@@ -109,6 +109,8 @@ av_cold void ff_pixblockdsp_init(PixblockDSPContext *c, AVCodecContext *avctx)
     ff_pixblockdsp_init_arm(c, avctx, high_bit_depth);
 #elif ARCH_PPC
     ff_pixblockdsp_init_ppc(c, avctx, high_bit_depth);
+#elif ARCH_RISCV
+    ff_pixblockdsp_init_riscv(c, avctx, high_bit_depth);
 #elif ARCH_X86
     ff_pixblockdsp_init_x86(c, avctx, high_bit_depth);
 #elif ARCH_MIPS
diff --git a/libavcodec/pixblockdsp.h b/libavcodec/pixblockdsp.h
index 07c2ec4f40..9b002aa3d6 100644
--- a/libavcodec/pixblockdsp.h
+++ b/libavcodec/pixblockdsp.h
@@ -52,6 +52,8 @@ void ff_pixblockdsp_init_arm(PixblockDSPContext *c, AVCodecContext *avctx,
                              unsigned high_bit_depth);
 void ff_pixblockdsp_init_ppc(PixblockDSPContext *c, AVCodecContext *avctx,
                              unsigned high_bit_depth);
+void ff_pixblockdsp_init_riscv(PixblockDSPContext *c, AVCodecContext *avctx,
+                               unsigned high_bit_depth);
 void ff_pixblockdsp_init_x86(PixblockDSPContext *c, AVCodecContext *avctx,
                              unsigned high_bit_depth);
 void ff_pixblockdsp_init_mips(PixblockDSPContext *c, AVCodecContext *avctx,
diff --git a/libavcodec/riscv/Makefile b/libavcodec/riscv/Makefile
index 414a9e9bd8..da07f1fe96 100644
--- a/libavcodec/riscv/Makefile
+++ b/libavcodec/riscv/Makefile
@@ -1,2 +1,4 @@
 OBJS-$(CONFIG_AUDIODSP) += riscv/audiodsp_init.o \
                            riscv/audiodsp_rvf.o
+OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_init.o \
+                              riscv/pixblockdsp_rvi.o
diff --git a/libavcodec/riscv/pixblockdsp_init.c b/libavcodec/riscv/pixblockdsp_init.c
new file mode 100644
index 0000000000..f489ec528b
--- /dev/null
+++ b/libavcodec/riscv/pixblockdsp_init.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+
+#include "libavutil/attributes.h"
+#include "libavutil/cpu.h"
+#include "libavcodec/avcodec.h"
+#include "libavcodec/pixblockdsp.h"
+
+void ff_get_pixels_8_rvi(int16_t *block, const uint8_t *pixels,
+                         ptrdiff_t stride);
+void ff_get_pixels_16_rvi(int16_t *block, const uint8_t *pixels,
+                          ptrdiff_t stride);
+
+av_cold void ff_pixblockdsp_init_riscv(PixblockDSPContext *c,
+                                       AVCodecContext *avctx,
+                                       unsigned high_bit_depth)
+{
+    int cpu_flags = av_get_cpu_flags();
+
+    if (cpu_flags & AV_CPU_FLAG_RVI) {
+        if (high_bit_depth)
+            c->get_pixels = ff_get_pixels_16_rvi;
+        else
+            c->get_pixels = ff_get_pixels_8_rvi;
+    }
+}
diff --git a/libavcodec/riscv/pixblockdsp_rvi.S b/libavcodec/riscv/pixblockdsp_rvi.S
new file mode 100644
index 0000000000..dbf51b0ad9
--- /dev/null
+++ b/libavcodec/riscv/pixblockdsp_rvi.S
@@ -0,0 +1,57 @@
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "config.h"
+#include "../libavutil/riscv/asm.S"
+
+func ff_get_pixels_8_rvi
+.irp row, 0, 1, 2, 3, 4, 5, 6, 7
+        ld      t0,    (a1)
+        add     a1, a1, a2
+        sd      zero, ((\row * 16) + 0)(a0)
+        addi    t6, t6, -1
+        sd      zero, ((\row * 16) + 8)(a0)
+        srli    t1, t0, 8
+        sb      t0, ((\row * 16) + 0)(a0)
+        srli    t2, t0, 16
+        sb      t1, ((\row * 16) + 2)(a0)
+        srli    t3, t0, 24
+        sb      t2, ((\row * 16) + 4)(a0)
+        srli    t4, t0, 32
+        sb      t3, ((\row * 16) + 6)(a0)
+        srli    t1, t0, 40
+        sb      t4, ((\row * 16) + 8)(a0)
+        srli    t2, t0, 48
+        sb      t1, ((\row * 16) + 10)(a0)
+        srli    t3, t0, 56
+        sb      t2, ((\row * 16) + 12)(a0)
+        sb      t3, ((\row * 16) + 14)(a0)
+.endr
+        ret
+endfunc
+
+func ff_get_pixels_16_rvi
+.irp row, 0, 1, 2, 3, 4, 5, 6, 7
+        ld      t0, 0(a1)
+        ld      t1, 8(a1)
+        add     a1, a1, a2
+        sd      t0, ((\row * 16) + 0)(a0)
+        sd      t1, ((\row * 16) + 8)(a0)
+.endr
+        ret
+endfunc
-- 
2.37.2

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^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-09-17 12:46 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-17 12:45 [FFmpeg-devel] [PATCHv2 0/6] RISC-V CPU extensions Rémi Denis-Courmont
2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 1/6] lavu/cpu: detect RISC-V base extensions remi
2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 2/6] lavu/cpu: CPU flags for the RISC-V Vector extension remi
2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 3/6] configure: probe " remi
2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 4/6] lavu/riscv: initial common header for assembler macros remi
2022-09-17 12:45 ` [FFmpeg-devel] [PATCH 5/6] lavc/audiodsp: add RISC-V F float vector clip remi
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