From: remi@remlab.net
To: ffmpeg-devel@ffmpeg.org
Subject: [FFmpeg-devel] [PATCH 12/18] lavu/riscv: float vector multiply-accumulate with RVV
Date: Fri, 9 Sep 2022 18:48:53 +0300
Message-ID: <20220909154859.68954-12-remi@remlab.net> (raw)
From: Rémi Denis-Courmont <remi@remlab.net>
---
libavutil/riscv/float_dsp_init.c | 6 +++++
libavutil/riscv/float_dsp_rvv.S | 38 ++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index 49a4c95a0b..b63da72acd 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -24,11 +24,15 @@
void ff_vector_fmul_rvv(float *dst, const float *src0, const float *src1,
int len);
+void ff_vector_fmac_scalar_rvv(float *dst, const float *src, float mul,
+ int len);
void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
int len);
void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1,
int len);
+void ff_vector_dmac_scalar_rvv(double *dst, const double *src, double mul,
+ int len);
void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
int len);
@@ -39,10 +43,12 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
if (flags & AV_CPU_FLAG_ZVE32F) {
fdsp->vector_fmul = ff_vector_fmul_rvv;
+ fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_rvv;
fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
if (flags & AV_CPU_FLAG_ZVE64D) {
fdsp->vector_dmul = ff_vector_dmul_rvv;
+ fdsp->vector_dmac_scalar = ff_vector_dmac_scalar_rvv;
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
}
}
diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index 65c3a77b01..5a7d92abd6 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -36,6 +36,25 @@ func ff_vector_fmul_rvv, zve32f
ret
endfunc
+// (a0) += (a1) * fa0 [0..a2-1]
+func ff_vector_fmac_scalar_rvv, zve32f
+NOHWF fmv.w.x fa0, a2
+NOHWF mv a2, a3
+
+1: vsetvli t0, a2, e32, m8, ta, ma
+ slli t1, t0, 2
+ vle32.v v24, (a1)
+ add a1, a1, t1
+ vle32.v v16, (a0)
+ vfmacc.vf v16, fa0, v24
+ sub a2, a2, t0
+ vse32.v v16, (a0)
+ add a0, a0, t1
+ bnez a2, 1b
+
+ ret
+endfunc
+
// (a0) = (a1) * fa0 [0..a2-1]
func ff_vector_fmul_scalar_rvv, zve32f
NOHWF fmv.w.x fa0, a2
@@ -71,6 +90,25 @@ func ff_vector_dmul_rvv, zve64d
ret
endfunc
+// (a0) += (a1) * fa0 [0..a2-1]
+func ff_vector_dmac_scalar_rvv, zve64d
+NOHWD fmv.d.x fa0, a2
+NOHWD mv a2, a3
+
+1: vsetvli t0, a2, e64, m8, ta, ma
+ slli t1, t0, 3
+ vle64.v v24, (a1)
+ add a1, a1, t1
+ vle64.v v16, (a0)
+ vfmacc.vf v16, fa0, v24
+ sub a2, a2, t0
+ vse64.v v16, (a0)
+ add a0, a0, t1
+ bnez a2, 1b
+
+ ret
+endfunc
+
// (a0) = (a1) * fa0 [0..a2-1]
func ff_vector_dmul_scalar_rvv, zve64d
NOHWD fmv.d.x fa0, a2
--
2.37.2
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next reply other threads:[~2022-09-09 15:51 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-09 15:48 remi [this message]
[not found] <2652141.mvXUDI8C0e@basile.remlab.net>
2022-09-12 15:53 ` remi
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