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* [FFmpeg-devel] [PATCH 11/18] lavu/riscv: float vector-vector multiplication with RVV
@ 2022-09-09 15:48 remi
  0 siblings, 0 replies; 2+ messages in thread
From: remi @ 2022-09-09 15:48 UTC (permalink / raw)
  To: ffmpeg-devel

From: Rémi Denis-Courmont <remi@remlab.net>

---
 libavutil/riscv/float_dsp_init.c |  9 ++++++++-
 libavutil/riscv/float_dsp_rvv.S  | 34 ++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index 7c553e9173..49a4c95a0b 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -22,9 +22,13 @@
 #include "libavutil/cpu.h"
 #include "libavutil/float_dsp.h"
 
+void ff_vector_fmul_rvv(float *dst, const float *src0, const float *src1,
+                         int len);
 void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
                                 int len);
 
+void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1,
+                         int len);
 void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
                                 int len);
 
@@ -34,10 +38,13 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
     int flags = av_get_cpu_flags();
 
     if (flags & AV_CPU_FLAG_ZVE32F) {
+        fdsp->vector_fmul = ff_vector_fmul_rvv;
         fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
 
-        if (flags & AV_CPU_FLAG_ZVE64D)
+        if (flags & AV_CPU_FLAG_ZVE64D) {
+            fdsp->vector_dmul = ff_vector_dmul_rvv;
             fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
+        }
     }
 #endif
 }
diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index 365e00190c..65c3a77b01 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -19,6 +19,23 @@
 #include "config.h"
 #include "asm.S"
 
+// (a0) = (a1) * (a2) [0..a3-1]
+func ff_vector_fmul_rvv, zve32f
+1:      vsetvli  t0, a3, e32, m8, ta, ma
+        slli     t1, t0, 2
+        vle32.v  v16, (a1)
+        add      a1, a1, t1
+        vle32.v  v24, (a2)
+        add      a2, a2, t1
+        vfmul.vv v16, v16, v24
+        sub      a3, a3, t0
+        vse32.v  v16, (a0)
+        add      a0, a0, t1
+        bnez     a3, 1b
+
+        ret
+endfunc
+
 // (a0) = (a1) * fa0 [0..a2-1]
 func ff_vector_fmul_scalar_rvv, zve32f
 NOHWF   fmv.w.x  fa0, a2
@@ -37,6 +54,23 @@ NOHWF   mv       a2, a3
         ret
 endfunc
 
+// (a0) = (a1) * (a2) [0..a3-1]
+func ff_vector_dmul_rvv, zve64d
+1:      vsetvli  t0, a3, e64, m8, ta, ma
+        slli     t1, t0, 3
+        vle64.v  v16, (a1)
+        add      a1, a1, t1
+        vle64.v  v24, (a2)
+        add      a2, a2, t1
+        vfmul.vv v16, v16, v24
+        sub      a3, a3, t0
+        vse64.v  v16, (a0)
+        add      a0, a0, t1
+        bnez     a3, 1b
+
+        ret
+endfunc
+
 // (a0) = (a1) * fa0 [0..a2-1]
 func ff_vector_dmul_scalar_rvv, zve64d
 NOHWD   fmv.d.x  fa0, a2
-- 
2.37.2

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^ permalink raw reply	[flat|nested] 2+ messages in thread
[parent not found: <2652141.mvXUDI8C0e@basile.remlab.net>]
end of thread, other threads:[~2022-09-12 15:55 UTC | newest]

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2022-09-09 15:48 [FFmpeg-devel] [PATCH 11/18] lavu/riscv: float vector-vector multiplication with RVV remi
     [not found] <2652141.mvXUDI8C0e@basile.remlab.net>
2022-09-12 15:53 ` remi

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