From: "Rémi Denis-Courmont" <remi@remlab.net>
To: ffmpeg-devel@ffmpeg.org
Subject: Re: [FFmpeg-devel] [PATCH] af_afir: RISC-V V fcmul_add
Date: Tue, 26 Sep 2023 21:50:53 +0300
Message-ID: <14015870.uCmUoPjYnm@basile.remlab.net> (raw)
In-Reply-To: <CAEa-L+u=vAHtbUBDMZE14MyUMOKkUpU5NyxkSNxBKNVwgzXswg@mail.gmail.com>
Le tiistaina 26. syyskuuta 2023, 12.24.58 EEST flow gg a écrit :
> benchmark:
> fcmul_add_c: 19.7
> fcmul_add_rvv_f32: 6.7
+ li t1, 4
+ vsetvli t0, t1, e32, m1, ta, ma
vsetivli t0, 4, ...
But really, DO NOT use a fixed vector length here. At best, you're wasting half
the vector width. Your input has a variable size, use it.
+
+ li t2, 8
+
+ vlsseg2e32.v v0, (a1), t2
I'm not sure what you are trying to achieve here. It seems that you could just
as well use vlseg2 without register stride, no?
+ vlsseg2e32.v v2, (a2), t2
+ vlsseg2e32.v v4, (a0), t2
+
+ vfmul.vv v6, v0, v2
+ vfmul.vv v7, v1, v3
+ vfmul.vv v8, v0, v3
+ vfmul.vv v9, v1, v2
+
+ vfadd.vv v4, v4, v6
+ vfsub.vv v4, v4, v7
+ vfadd.vv v5, v5, v8
+ vfadd.vv v5, v5, v9
+
+ vssseg2e32.v v4, (a0), t2
Same here.
--
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next prev parent reply other threads:[~2023-09-26 18:51 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-26 9:24 flow gg
2023-09-26 18:34 ` Rémi Denis-Courmont
2023-09-26 18:40 ` Paul B Mahol
2023-09-26 18:44 ` Rémi Denis-Courmont
2023-09-27 1:47 ` flow gg
2023-09-27 16:01 ` Rémi Denis-Courmont
2023-09-27 16:27 ` Rémi Denis-Courmont
2023-09-26 18:50 ` Rémi Denis-Courmont [this message]
2023-09-27 16:41 ` Rémi Denis-Courmont
2023-09-28 5:45 ` flow gg
2023-09-28 13:33 ` Rémi Denis-Courmont
2023-11-13 9:43 ` flow gg
2023-11-13 15:35 ` Rémi Denis-Courmont
2023-11-13 16:01 ` Paul B Mahol
2023-11-15 8:57 ` flow gg
2023-11-15 8:59 ` flow gg
2023-11-15 15:05 ` Rémi Denis-Courmont
2023-11-15 23:04 ` flow gg
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